18
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
Signals
This section describes the signals used by the L64118.
Figure 3 shows
the L64118 non-GPIO mode signals in functional groups and
Figure 4shows the L64118 GPIO mode signals. The signals are described by
group. Within each group, signals are listed in alphabetic order.
0xA000.0000
0x8000.0000
0x0000.0000
Primary SDRAM
when 2 Mbytes of
SDRAM is used
0x0000.0000
(PBus)
2
0xA000.0000
0x8000.0000
0x0000.0000
Primary SDRAM
when 8 or
16 Mbytes of
SDRAM is used
0x0100.0000
(PBus)
8or16
1. These transactions do not appear on the PBus. This space is used only when the CPU accesses
BBus components (BBCC, Timer, C2P, INTC, ICEport).
2. Within this range, used for 8-bit devices, specic address ranges can be selected (and the mode in
which they are accessed) using the Ebus address compare registers.
3. Bits [23:0] of the BBus address are reected onto the EBus Address bus for eight-bit devices.
4. Within this range used for 16-bit devices, specic address ranges can be selected (and the mode
in which they are accessed) using the EBus Address Compare registers.
5. Bits [23:0] of the BBus address are reected onto the EBus Address bus for 16-bit devices.
6. Within this range used for 32-bit devices, specic address ranges can be selected (and the mode
in which they are accessed) using the EBus Address Compare registers.
7. Same address used on the EBus and BBus when 32-bit devices are accessed.
Table 3
L64118 Address Mapping (Cont.)
Virtual CPU Base Address
BBus Base
Address
Address Space
Name
PBus/EBus
Physical
Base
Address
Size
(Mbytes)
Noncache
kseg1
Cache
kseg0
118bds Page 18 Wednesday, February 3, 1999 12:37 PM