參數(shù)資料
型號(hào)： L64118
廠商： LSI CORP
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA256
封裝： PLASTIC, BGA-256
文件頁(yè)數(shù)： 30/68頁(yè)
文件大?。?/td> 877K
代理商： L64118
36
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
clocked in to the external A/V decoder. Deassertion of
VREQn indicates that the A/V decoder is not ready to
accept video data.
VVALID
Video Data Valid
Output
When asserted, this signal indicates that valid video data
is available on the AVD line. The LOW-to-HIGH transition
of SCLK causes the video data bit on the AVD[7:0] bus
to be latched in the external A/V decoder. In serial mode,
VVALID is active HIGH. In parallel mode, VVALID latches
data on the rising edge. This signal is not asserted after
reset.
Audio Clock Generator
These signals generate the oversampling audio clock, which drives the
L64105 external A/V decoder and a low-cost audio DAC. The audio clock
generation circuit provides oversampling audio frequencies locked to the
27 MHz program clock. The fully programmable circuit supports a wide
range of oversampling audio frequencies. It is implemented using
advanced mixed-signal technology.
ACLK
Audio Clock
Output
ACLK provides the oversampling audio clock that drives
the L64105 audio clock input and the system clock input
pin of conventional stereo audio DAC. This signal is
driven LOW after reset.
AVDD
Analog VDD 3.3 V
Input
AVDD provides the power voltage to the analog circuit of
the audio clock generator. It must be isolated from the
Digital VDD (DVDD) by a 10
H ferrite insulator.
AVSS
Analog Ground
Input
AVSS provides the analog ground to the audio clock
generator circuit. It should must be isolated from the
digital ground supply (DGND).
IREF
Current Reference
This pin must be connected as shown in Figure 5.
118bds Page 36 Wednesday, February 3, 1999 12:37 PM
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