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參數(shù)資料
| 型號： | L64118 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 28/68頁 |
| 文件大?。?/td> | 877K |
| 代理商： | L64118 |
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34
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
SBD[15:0]
SDRAM Data Bus
Bidirectional
This data bus is driven by the SDRAM during a read
operation, and driven by the L64118 during a write
operation. It is 3-stated after reset and when there are no
memory accesses.
SCASn
Column Address Strobe
Output
This signal is the active LOW column address strobe. It
is used in conjunction with the SRASn and SWEn outputs
to form the SDRAM command.
SDCLK
SDRAM Clock
Output
This is the master SDRAM clock. All output signals are
referenced to the rising edge of SDCLK. The
programmable SDRAM timing parameters are expressed
in SDCLK periods.
SDQMH
High Byte Mask
Output
This active HIGH signal is the high byte data mask, which
controls the high byte input/output buffer of the external
SDRAM. When asserted, it disables (masks) the high
data byte of the SDRAM data bus.
GPIO6
Bidirectional
SDQMH can serve as a general-purpose I/O signal
(GPIO6) by setting bit [0] in the General-Purpose Mode
register.
SDQML
Low Byte Mask
Output
This active HIGH signal is the low byte data mask, which
controls the low byte input/output buffer of the external
SDRAM. When asserted, it disables (masks) the low data
byte of the SDRAM data bus.
SRASn
Row Address Strobe
Output
This signal is the active LOW row address strobe. SRASn
is used in conjunction with the SCASn and SWEn outputs
to form the SDRAM command.
SWEn
Write Enable
Output
This signal is the active LOW write enable strobe. SWEn
is used in conjunction with the SRASn and SCASn
outputs to form the SDRAM command.
118bds Page 34 Wednesday, February 3, 1999 12:37 PM
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