參數(shù)資料
型號(hào)： L64118
廠商： LSI CORP
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA256
封裝： PLASTIC, BGA-256
文件頁(yè)數(shù)： 35/68頁(yè)
文件大?。?/td> 877K
代理商： L64118
40
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
Aux - Packet ID [2]
Output
In Aux mode, this signal is part of a three-bit packet ID
that can be assigned to PIDs that are output to the Aux
port.
GPIO25
Bidirectional
This signal can also serve as a general-purpose I/O
signal (GPIO25) by setting bit 3 in the General-Purpose
Mode register.
PDATA[7:0]
Parallel I/O Data Signals
1284
Bidirectional
In 1284 mode, these signals carry the data transferred
between the host and the IEEE1284 port.
Aux
Bidirectional
In Aux mode, PDATA[7:0] carry the transport packets
from/to the L64118 demultiplexer and the Aux port.
GPIO[23:16]
Bidirectional
These signals can also serve as a general-purpose I/O
bus (GPIO[23:16]) by setting bit 3 in the General-Purpose
Mode register.
By default, this signal is not asserted after reset.
PDATA_DIR/OP_MODE[2]
1284 - Peripheral Data Direction
Output
After reset, this signal serves as the PDATA_DIR output
signal that controls the parallel data bus buffers in 1284
mode. In Aux mode, this pin is driven HIGH.
Operational Mode 2
Input
This signal is used as a strap option during reset. For
normal device operation, use a 10 k
to pull this signal
LOW during reset.
PERROR/AUXPID[0]
1284 - Peripheral Error
Output
In 1284 mode, this signal functions as PERROR. When
HIGH, this signal indicates that the L64118 IEEE1284
port encountered an error during the data processing.
FAULTn is asserted whenever PERROR is activated.
118bds Page 40 Wednesday, February 3, 1999 12:37 PM
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