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參數(shù)資料
| 型號： | L64118 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 29/68頁 |
| 文件大?。?/td> | 877K |
| 代理商： | L64118 |
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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 35
Audio/Video Decoder Port
These signals provide the interface between the L64118 and an external
MPEG-2 Audio/Video decoder. This interface supports a seamless
connection between the L64118 and LSI Logic’s L64105 A/V decoders.
It supports a serial data transfer rate up to 27 Mbits/s in serial mode,
9 Mbytes/s in parallel mode. The actual data rate is controlled by the
audio and video request signals coming out from the A/V decoder device.
AREQn
Audio Data Request
Input
When asserted, this signal indicates that the external
A/V decoder is requesting the audio bit to be clocked in
to the external A/V decoder. Deassertion of AREQn
indicates that the A/V decoder is not ready to accept
audio data.
AVALID
Audio Data Valid
Output
When asserted, this signal indicates that valid audio data
is available on the AVD[7:0] bus. A LOW-to-HIGH
transition of SCLK causes the audio data bit on AVD to
be latched in the external A/V decoder. In serial mode,
AVALID is active HIGH. In parallel mode, AVALID latches
data on the rising edge. This signal is not asserted after
reset.
AVD[7:0]
Audio Video Compressed Data
Bidirectional
This bus provides data to the external A/V decoder. In
serial mode, AVD[0] carries the data. In parallel mode,
the entire bus carries the byte-wide data. The L64118
outputs PES audio and video data from the on-chip
buffers and SDRAM buffers through AVD[7:0]. These
signals drive an unknown value after reset.
AVERRn
Audio Video Data Error
Output
When asserted, this signal indicates that there is an
uncorrected error in the bit stream entering the external
A/V decoder. The L64118 generates AVERRn as a result
of detection of discontinuity in the transport packets of the
audio and/or video program being decoded. Usually, the
discontinuity is the result of loss of packets from
uncorrected errors. This signal is not asserted after reset.
VREQn
Video Data Request
Input
When asserted, this signal indicates that the external
A/V decoder device is requesting the video bit to be
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