參數(shù)資料
型號： L6460TR
廠商： STMICROELECTRONICS
元件分類： 運動控制電子
英文描述： STEPPER MOTOR CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 12/139頁
文件大小： 3837K
代理商： L6460TR
L6460
GPIO pins
Doc ID 17713 Rev 1
109/139
22.6
GPIO[5]
The GPIO[5] truth table is (for the abbreviation list please refer to Table 40).
Table 46.
GPIO[5] truth table
Master(1)
1.
Master bit is at logic level “1” when
L6460 is used as a master device (seeChapter 8)
AUX1
system
and
Vloop1
external(2)
2.
This bit is at logic level “1” if AUX1 regulator is a system regulator but its power stage is externally realized
(and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic
level “1”, while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level “0” in
CoreConfigReg register.
GPIO[5] SPI BITS
Function
Note
GpioOut
enable[5]
Mode[2]
Mode[1]
Mode[0]
1
X
Slave control
0
1
X
Reg Loop1 OUT
(3)
3.
In all configurations in which GPIO[5] is enabled as output:
a) the GPIO[5] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[5] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c)
the GPIO[5] pin is a rail to rail, back to back output supplied by V3v3.
0
X
HiZ (SPI_IN)
0
1
0
SPI OUT
00
1
0
1
Comp1OUT
0
1
0
1
0
Reg Loop1 OUT
0
1
0
1
AuxPwm3
0
1
0
SPI OUT inverted
0
1
0
1
Comp1OUT inverted
00
1
0
Reg Loop1 OUT
inverted
0
1
AuxPwm3 inverted
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