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| 型號： | LAN83C185-JT |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64 |
| 文件頁數(shù)： | 17/61頁 |
| 文件大?。?/td> | 459K |
| 代理商： | LAN83C185-JT |
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Chapter 4 Architecture Details
SMSC LAN83C185
17
Rev. 0.8 (11-16-04)
DATASHEET
4.1
Top Level Functional Architecture
Functionally, the PHY can be divided into the following sections:
■
100Base-TX transmit and receive
■
10Base-T transmit and receive
■
MII interface to the controller
■
Auto-negotiation to automatically determine the best speed and duplex possible
■
Management Control to read status registers and write control registers
Figure 4.1
100Base-TX Data Path
4.2
100Base-TX Transmit
The data path of the 100Base-TX is shown in
Figure 4.1
. Each major block is explained below.
4.2.1
100M Transmit Data across the MII
The MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate valid
data. The data is latched by the PHY’s MII block on the rising edge of TX_CLK. The data is in the
form of 4-bit wide 25MHz data.
4.2.2
4B/5B Encoding
The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from
4-bit nibbles to 5-bit symbols (known as “code-groups”) according to
Table 4.1
. Each 4-bit data-nibble
is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for
control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles,
0 through F. The remaining code-groups are given letter designations with slashes on either side. For
example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.
MAC
Tx
Driver
MLT-3
Converter
NRZI
Converter
4B/5B
Encoder
Magnetics
CAT-5
RJ45
100M
PLL
MII 25 MHz by 4 bits
TX_CLK
(for MII)
25MHz by
5 bits
NRZI
MLT-3
MLT-3
MLT-3
MLT-3
Scrambler
and PISO
125 Mbps Serial
MII
25MHz
by 4 bits
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