參數(shù)資料
型號(hào)： LAN83C185-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 網(wǎng)絡(luò)接口
英文描述： HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 9/61頁(yè)
文件大小： 459K
代理商： LAN83C185-JT
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Chapter 1 General Description
SMSC LAN83C185
9
Rev. 0.8 (11-16-04)
DATASHEET
The SMSC LAN83C185 is a low-power, highly integrated analog interface IC for high-performance
embedded Ethernet applications. The LAN83C185 requires only a single +3.3V supply.
The LAN83C185 consists of an encoder/decoder, scrambler/descrambler, transmitter with wave-
shaping and output driver, twisted-pair receiver with on-chip adaptive equalizer and baseline wander
(BLW) correction, clock and data recovery, and Media Independent Interface (MII).
The LAN83C185 is fully compliant with IEEE 802.3/ 802.3u standards and supports both 802.3u-
compliant and vendor-specific register functions. It contains a full-duplex 10-BASET/100BASE-TX
transceiver and supports 10-Mbps (10BASE-T) operation on Category 3 and Category 5 unshielded
twisted-pair cable, and 100-Mbps (100BASE-TX) operation on Category 5 unshielded twisted-pair
cable.
1.1
Architectural Overview
Figure 1.1 LAN83C185 Architectural Overview
10M Rx
Logic
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
Analog-to-
Digital
100M PLL
Squelch &
Filters
10M PLL
Receive Section
Central
Bias
Auto-
Negotiation
Management
Control
SMI
M
TXP / TXN
TXD[0..3]
TX_EN
TX_ER
TX_CLK
RXD[0..3]
RX_DV
RX_ER
RX_CLK
CRS
COL
MDC
MDIO
SPEED100
LINKON
ACTIVITY
FDUPLEX
LED Circuitry
GPO Circuitry
MODE Control
GPO0
GPO1
GPO2
nINT
nRESET
RXP / RXN
10M Tx
Logic
10M
Transmitter
100M Tx
Logic
100M
Transmitter
Transmit Section
PLL
XTAL1
XTAL2
MODE0
MODE1
MODE2
PHY
Address
Latches
PHYAD[0..4]
1.8V
Regulator
Interrupt
Generator
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