參數(shù)資料
型號(hào)： LAN83C185-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 39/61頁(yè)
文件大?。?/td> 459K
代理商： LAN83C185-JT
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
39
Rev. 0.8 (11-16-04)
DATASHEET
17.8
FASTEST
Auto-Negotiation Test Mode
0 = normal operation
1 = activates test mode
RW
0
17.7:5
Reserved
Write as 0, ignore on read.
17.4
Reserved
Reserved
Must be left at 0
RW
0
17.3
PHYADBP
1 = PHY disregards PHY address in SMI access
write.
RW
0
17.2
Force
Good Link Status
0 = normal operation;
1 = force 100TX- link active;
Note:
This bit should be set only during lab testing
RW
0
17.1
ENERGYON
ENERGYON – indicates whether energy is detected
on the line (see
Section 5.4.5.2, "Energy Detect
Power-Down," on page 44
); it goes to “0” if no valid
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
RO
1
17.0
Reserved
Write as “0”. Ignore on read.
RW
0
Table 5.43 Register 18 - Special Modes
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
18.15:14
MIIMODE
MII Mode
: set the mode of the MII:
0 – MII interface.
1 – Reserved
RW,
NASR
18.13
CLKSELFREQ
Clock In Selected Frequency. Set the requested input
clock frequency. This bit drives signal that goes to
external logic of the Phy and select the desired
frequency of the input clock:
0 – the clock frequency is 25MHz
1 – Reserved
RO,
NASR
18.12
DSPBP
DSP Bypass mode. Used only in special lab tests.
RW,
NASR
0
18.11
SQBP
SQUELCH Bypass mode.
RW,
NASR
0
18.10
Reserved
RW,
NASR
18.9
PLLBP
PLL Bypass mode.
RW,
NASR
18.8
ADCBP
ADC Bypass mode.
RW,
NASR
18.7:5
MODE
PHY Mode of operation. Refer to
Section 5.4.9.2,
"Mode Bus – MODE[2:0]," on page 47
for more
details.
RW,
NASR
Table 5.42 Register 17 - Mode Control/Status (continued)
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
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