參數(shù)資料
型號(hào)： LC5256MC-5F256C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： PLD
英文描述： 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
中文描述： EE PLD, 6 ns, PBGA256
封裝： FPBGA-256
文件頁(yè)數(shù)： 10/92頁(yè)
文件大?。?/td> 378K
代理商： LC5256MC-5F256C
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
10
True Dual-Port SRAM Mode
In Dual-Port SRAM Mode the multi-function array is con
fi
gured as a dual port SRAM. In this mode two independent
read/write ports access the same 8,192-bits of memory. Data widths of 1, 2, 4, 8, and 16 are supported by the
MFB. Figure 9 shows the block diagram of the dual port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Resets are asynchronous. All inputs on the same port share the same
clock, clock enable, and reset selections. All outputs on the same port share the same clock, clock enable, and
reset selections. Selections may be made independently between both inputs and outputs and ports. Table 5
shows the possible sources for the clock, clock enable and initialization signals for the various registers.
Figure 9. Dual-Port SRAM Block Diagram
Table 5. Register Clock, Clock Enable, and Reset in Dual-Port SRAM Mode
Register
Input
Source
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
Clock
CLKA (CLKB) or one of the global clocks (CLK0 - CLK3). The selected sig-
nal can be inverted if desired.
CENA (CENB) or one of the global clocks (CLK1 - CLK 2). The selected sig-
nal can be inverted if required.
Created by the logical OR of the global reset signal and RSTA (RSTB).
RSTA (RSTB) can be inverted is desired.
Clock Enable
Reset
‘
‘
Read/Write Address
(ADA[0:8-12]
)
Clock A
(CLKA)
Write/Read A
(WRA)
Chip Sel A
(CSA [0:1])
Reset A
(RSTA)
68 Inputs
From
Routing
Dual
Port
SRAM
Array
PORT
A
PORT B
Similar signals
as PORT A:
ADB[0:8-12], RSTB,
CLKB, CENB, WRB,
CSB[0,1], DIB[0:0,1,3,7,15]
Write Data
(DIA[0:0,1,3,7,15]
)
Clk En A
(CENA)
RESET
CLK0
CLK1
CLK2
RD Data A
(DOA[0:0-15]
)
RD Data B
(DOB[0:0-15]
)
相關(guān)PDF資料
PDF描述
LC5256MC-75F256C 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-45F256C 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-45F484C 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
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LC5512MC-75F256C 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5256MC-5F256I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5256MC-5F484C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5256MC-5F484I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5256MC-5F672C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5256MC-5F672I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
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