參數(shù)資料
型號: LC5256MC-5F256C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
中文描述: EE PLD, 6 ns, PBGA256
封裝: FPBGA-256
文件頁數(shù): 23/92頁
文件大?。?/td> 378K
代理商: LC5256MC-5F256C
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
23
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min.
Typ.
Max.
10
40
Units
μA
μA
I
IL,
I
IH
1
Input or I/O Leakage
0
V
IN
(V
CCO
- 0.2V)
(V
CCO
- 0.2V) < V
IN
3.6V
3.6V < V
IN
5.5V and
3.0V
V
CCO
3.6V
0
V
IN
0.7 V
CCO
V
IL
(MAX)
V
IN
V
IH
(MAX)
V
IN
= V
IL
(MAX)
I
IH
4
Input High Leakage Current
3
mA
I
PU
I
PD
I
BHLS
I
BHHS
I
BHLO
I
BHHO
V
BHT
3
I/O Active Pullup Current
I/O Active Pulldown Current
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current V
IN
= 0.7 V
CCO
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
-30
30
30
30
8
8
8
8
8
8
-150
150
150
150
μA
μA
μA
μA
μA
μA
μA
pf
pf
pf
pf
pf
pf
0
V
IN
V
IH
(MAX)
0
V
IN
V
IH
(MAX)
0
V
IN
V
IH
(MAX)
V
CCO
= 3.3V, 2.5V, 1.8V
V
CC
= 1.8V, V
IO
= 0 to V
IH
(MAX)
V
CCO
= 3.3V, 2.5V, 1.8V
V
CC
= 1.8V, V
IO
= 0 to V
IH
(MAX)
V
CCO
= 3.3V, 2.5V, 1.8V
V
CC
= 1.8V, V
IO
= 0 to V
IH
(MAX)
V
CCO
* 0.35
V
CCO
* 0.65
C1
I/O Capacitance
2
C2
Clock Capacitance
2
C3
Global Input Capacitance
2
1. Input or I/O leakage current is measured with the pin con
fi
gured as an input or as an I/O with the output driver tristated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. T
A
25°C, f=1.0MHz
3. I
PU
on JTAG pins has a maximum of -175μA for 5512MX devices.
4. 5V tolerant inputs and I/Os should be placed in banks where 3.0V
V
CCO
3.6V. The JTAG and sysCONFIG ports are not included for the
5V tolerant interface.
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