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參數(shù)資料
| 型號： | LCK4950 |
| 英文描述： | Low-Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時鐘驅(qū)動器 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 215K |
| 代理商： | LCK4950 |
Agere Systems Inc.
13
Data Sheet
November 2001
Low-Voltage PLL Clock Driver
LCK4950
Electrical Characteristics
(continued)
5-9708 (F)
Figure 9. PLL Block Diagram
Note:
For computations refer to the following equations:
m = 8 (FBsel = 1), 16(FBsel = 0), P = 1
For the LCK4950 clock driver, the following will provide an example of how to determine the crystal frequency
required for a given design.
Given:
Qa = 160 MHz
Qb = 80 MHz
Qc = 40 MHz
Qd = 40 MHz
FBSel = 0
(eq. 1)
From Figure 3:
fQd = V
CO
/8 then N = 8 or fQa = V
CO
/2 then N = 2
From Figure 9:
m = 16 and P = 1
or
PHASE
DETECTOR
LPF
V
CO
÷
P
÷
N
÷
m
Qn
f
ref
f
m
-------------
f
vco
fQ
=
,
=
f
ref
fQn
N
P
m
=
∴
f
ref
fQn
N
P
m
=
t
ref
40
8
1
16
20 MHz
=
=
t
ref
160
2
1
16
20 MHz
=
=
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