參數(shù)資料
型號(hào): LCK4950
英文描述: Low-Voltage PLL Clock Driver
中文描述: 低電壓PLL時(shí)鐘驅(qū)動(dòng)器
文件頁(yè)數(shù): 8/16頁(yè)
文件大?。?/td> 215K
代理商: LCK4950
8
Agere Systems Inc.
Data Sheet
November 2001
Low-Voltage PLL Clock Driver
LCK4950
Electrical Characteristics
Table 7. dc Characteristics
T
A
= 0
°
C to 70
°
C, V
CC
= 3.3 V ± 5%.
Table 8. ac Characteristics
T
A
= 0
°
C to 70
°
C, V
CC
= 3.3 V ± 5%.
Characteristic
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
C
IN
C
pd
I
DDQ
Min
2.0
2.4
Typ
25
Max
3.6
0.8
0.5
±120
4
1
Unit
V
V
V
V
μA
pF
pF
mA
Condition
I
OH
=
40 mA
1
I
OL
= 40 mA
1
Input High Voltage (LVCMOS inputs)
Input Low Voltage (LVCMOS inputs)
Output High Voltage
Output Low Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum Quiescent Supply Current
Non-PLL
Maximum PLL Supply Current
1. The LCK4950 outputs can drive series or parallel-terminated 50
(or 50
to V
CC
/2) transmission lines on the incident edge.
2. Total power = (I
DDPLL
+ I
DDQ
) x V + (fQaCQa + fQbCQb + fQc0CQc0 + fQc1CQc1 + fQd0CQd0 + fQd1CQd1 + fQd2CQd2 + fQd3CQd3 +
fQd4CQd4) x V
2
; where V = V
DD, CQa
= load capacitance on Qa, CQb = load capacitance on Qb, etc.
Per Output
All V
DD
Pins
Except V
DDA2
V
DDA
Pin Only
I
DDPLL
55
mA
Characteristic
Symbol
t
r
, t
f
t
pw
t
sk(0)
Min
0.10
48.5
Typ
Max
1.0
52.5
Unit
ns
%
Condition
0.8 V to 2.0 V
Output Rise/Fall Time
Output Duty Cycle
Same Frequencies
Output-to-Output Skews
Different Frequencies:
Qa
fmax
< 150 MHz
Qa
fmax
> 150 MHz
PLL V
CO
(feedback = V
CO
/4)
Lock (feedback = V
CO
/8)
Range (feedback = V
CO
/16)
Maximum Output Frequency:
Qa(
÷
2)
Qa/Qb (
÷
4)
Qb (
÷
8)
Output Disable Time
Output Enable Time
Cycle-to-Cycle Jitter (peak-to-peak)
Maximum PLL Clock Time
150
300
ps
200
200
200
200
400
400
480
480
480
ps
ps
MHz
MHz
MHz
f
VCO
f
max
±35
180
120
60
7
6
±50
10
MHz
MHz
MHz
ns
ns
ps
ms
1
t
PLZ,HZ
t
PZL
t
jitter
t
lock
1.See Applications section for more information.
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