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參數(shù)資料
| 型號： | LCK4950 |
| 英文描述： | Low-Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 215K |
| 代理商： | LCK4950 |
Agere Systems Inc.
5
Data Sheet
November 2001
Low-Voltage PLL Clock Driver
LCK4950
Applications
Programming the LCK4950S
Several frequency relationships are configurable by the LCK4950. Frequency ratios of 1:1, 2:1, 4:1, and 4:2:1 are
possible from configuring the output dividers for the four output groups. To ensure that the output duty cycle is
always 50%, the LCK4950 uses even dividers. Table 4 illustrates output configurations of the LCK4950, describing
the outputs using the V
CO
frequency as a reference. For example, setting the Qa outputs to V
CO
/2, the Qb and Qc
to V
CO
/4, and the Qd to V
CO
/8 would provide the output frequency relationship of 4:2:1.
Table 4. Programmable Output Frequency Relationships
The division settings establish the output relationship, but one must still ensure that the V
CO
will be stable given the
frequency of the outputs desired. The feedback frequency should be used to situate the V
CO
into a frequency
range in which the PLL will be stable. The design of the PLL is such that for output frequencies between 25 MHz
and 180 MHz, the LCK4950 can generally be configured into a stable region.
Inputs
Outputs
FSELA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FSELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FSELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Qa
Qb
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/8
V
CO
/8
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/8
V
CO
/8
Qc
Qd
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/4
V
CO
/8
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/2
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
V
CO
/4
V
CO
/4
V
CO
/8
V
CO
/8
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