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參數(shù)資料
| 型號(hào)： | LCK4950 |
| 英文描述： | Low-Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 215K |
| 代理商： | LCK4950 |
6
Agere Systems Inc.
Data Sheet
November 2001
Low-Voltage PLL Clock Driver
LCK4950
Applications
(continued)
Table 5. Input Reference vs. Output Frequency Relationships
The relationship between the input reference and the output frequency is very flexible. Table 5 shows the
multiplication factors between the inputs and outputs for the LCK4950. Figure 3 through Figure 6 illustrate several
programming possibilities.
Note:
The variations of the configurations shown are not complete, but do represent potential applications.
Config
fsela
fselb
fselc
fseld
FB_Sel = 1
FB_Sel = 0
Qa
4x
4x
4x
4x
4x
4x
4x
4x
2x
2x
2x
2x
2x
2x
2x
2x
Qb
2x
2x
2x
2x
x
x
x
x
2x
2x
2x
2x
x
x
x
x
Qc
2x
2x
x
x
2x
2x
x
x
2x
2x
x
x
2x
2x
x
x
Qd
2x
x
2x
x
2x
x
2x
x
2x
x
2x
x
2x
x
2x
x
Qa
8x
8x
8x
8x
8x
8x
8x
8x
4x
4x
4x
4x
4x
4x
4x
4x
Qb
4x
4x
4x
4x
2x
2x
2x
2x
4x
4x
4x
4x
2x
2x
2x
2x
Qc
4x
4x
2x
2x
4x
4x
2x
2x
4x
4x
2x
2x
4x
4x
2x
2x
Qd
4x
2x
4x
2x
4x
2x
4x
2x
4x
2x
4x
2x
4x
2x
4x
2x
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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