- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367540 > LCK4950 Low-Voltage PLL Clock Driver PDF資料下載
參數(shù)資料
| 型號(hào)： | LCK4950 |
| 英文描述： | Low-Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | LCK4950 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
Agere Systems Inc.
9
Data Sheet
November 2001
Low-Voltage PLL Clock Driver
LCK4950
Electrical Characteristics
(continued)
Jitter Performance of the LCK4950S
More focus is given to clock distribution design and management today because of the continuing increase of
today
’
s digital system
’
s clock rates. System-clock jitter and its effect on overall system timing budget is at the
center of this focus. The LCK4950 is designed to utilize a differential CMOS PLL and incorporate multiple power
and ground pins in the design to minimize clock jitter. The following text provides details on the jitter performance,
illustrates measurement limitations, and provides guidelines to minimize the jitter of the LCK4950.
The most commonly specified jitter parameter is cycle-to-cycle jitter. With today
’
s high-performance measurement
equipment, there is no way to measure this parameter for jitter performance in the class demonstrated by the
LCK4950. As a result, different methods are used which approximate cycle-to-cycle jitter. The typical method of
measuring the jitter is to accumulate a large number of cycles, create a histogram of the edge placements, and
record peak-to-peak as well as standard deviations of the jitter. It is of great importance to measure the edge
immediately following the trigger edge. If this is not the case, the measurement inaccuracy will add significantly to
the measured jitter. The oscilloscope cannot collect adjacent pulses. It is safe to assume that collecting pulse
information in this mode will produce jitter values somewhat larger than if consecutive cycles were measured;
therefore, this measurement will represent an upper bound of cycle-to-cycle jitter. Most likely, this is a conservative
estimate of the cycle-to-cycle jitter.
There are two common sources of jitter for a PLL-based clock driver. The most common source of jitter is random
jitter. Less commonly known is the jitter produced by different frequency outputs switching synchronously. If all of
the outputs are switching at the same frequency, the PLL jitter is equal to the total jitter of the device. In the
LCK4950, where a number of the outputs can be switching synchronously but at different frequencies, a
multimodal jitter distribution can be seen on the highest frequency outputs. It is important to consider what is
happening on the other outputs because the output being monitored is affected by the activity on the other outputs.
From Figure 7, one can see that for each rising edge on the higher-frequency signal, the activity on the lower-
frequency signal is not consistent.
The placement of the edge that is being monitored is displaced in time due to the activity on the other outputs
altering the internal thresholds of the device. The relationship is periodic because the signals are synchronous.
The resulting jitter is a superposition of the PLL jitter on the displaced edges. The multimodal distribution will
appear to be a fat Gaussian distribution, or a truly multimodal distribution depending on the size of the PLL jitter
and displacement of the edges. When all the outputs are switching at the same frequency, there is no edge
displacement and the jitter is that of the PLL.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LCK4953 | Low-Voltage PLL Clock Driver |
| LCS2W123.3W10 | Analog IC |
| LCS2W1233-10W | Analog IC |
| LCS2W243.3W10 | Analog IC |
| LCS2W2433-10W | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LCK4953 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Voltage PLL Clock Driver |
| LCK4972 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Voltage PLL Clock Driver |
| LCK4973 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Voltage PLL Clock Driver |
| LCK4993 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Voltage PLL Clock Drivers |
| LCK4993KB-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Voltage PLL Clock Drivers |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。