參數(shù)資料
型號: LH28F020SU-N
廠商: Sharp Corporation
英文描述: 2M (256K 】 8) Flash Memory
中文描述: 200萬(256K】8)閃存
文件頁數(shù): 19/31頁
文件大?。?/td> 245K
代理商: LH28F020SU-N
2M (256K × 8) Flash Memory
LH28F020SU-L
19
Timing Nomenclature
For 3.3 V systems use 1.5 V cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
t
CE
t
OE
t
ACC
t
AVQV
t
AS
t
DH
t
ELQV
t
GLQV
time (t) from CE
(E) going low (L) to the outputs (Q) becoming valid (V)
time (t) from OE
(G) going low (L) to the outputs (Q) becoming valid (V)
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
t
AVWH
t
WHDX
time (t) from address (A) valid (V) to WE
(W) going high (H)
time (t) from WE
(W) going high (H) to when the data (D) can become undefined (X)
PIN CHARACTERS
PIN STATES
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CE
(Chip Enable)
X
Driven, but not necessarily valid
G
OE
(Output Enable)
Z
High Impedance
W
WE (Write Enable)
V
Any Voltage Level
3 V
V
CC
at 3.0 V MIN.
Figure 14. Transient Input/Output
Reference Waveform (V
CC
= 3.3 V)
Figure 15. Transient Equivalent Testing
Load Circuit (V
CC
= 3.3 V)
INPUT
0.0
TEST POINTS
OUTPUT
3.0
1.5
1.5
28F020SUL15-13
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1'
and 0.0 V for a Logic '0'. Input timing begins
and output timing ends at 1.5 V. Input rise
and fall times (10% to 90%) < 10 ns.
2.5 ns OF 50
TRANSMISSION LINE
TOTAL CAPACITANCE = 50 pF
FROM OUTPUT
UNDER TEST
TEST
POINT
28F020SUL15-14
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