參數(shù)資料
型號(hào)： LH28F800SG-L10
廠商： Sharp Corporation
英文描述： 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
中文描述： 8 M位（512 KB的× 16）SmartVoltage閃存
文件頁(yè)數(shù)： 15/45頁(yè)
文件大?。?/td> 328K
代理商： LH28F800SG-L10
- 15 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
set block or permanent lock-bit setup along with
appropriate block or device address is written
followed by either the set block lock-bit confirm (and
an address within the block to be locked) or the set
permanent lock-bit confirm (and any device
address). The WSM then controls the set lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when
read (see
Fig. 7
). The CPU can detect the
completion of the set lock-bit event by analyzing the
RY/BY# pin output or status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Permanent Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations
occur only when V
CC
= V
CC1/2/3/4
and V
PP
=
V
PPH1/2/3
. In the absence of this high voltage, lock-
bit contents are protected against alteration.
A successful set block lock-bit operation requires
that the permanent lock-bit be cleared and WP# =
V
IH
or RP# = V
HH
. If it is attempted with the
permanent lock-bit set, SR.1 and SR.4 will be set
to "1" and the operation will fail. Set block lock-bit
operations while V
IH
< RP# < V
HH
produce
spurious results and should not be attempted. A
successful set permanent lock-bit operation requires
that RP# = V
HH
. If it is attempted with RP# = V
IH
,
SR.1 and SR.4 will be set to "1" and the operation
will fail. Set permanent lock-bit operations with V
IH
< RP# < V
HH
produce spurious results and should
not be attempted.
4.10 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the
permanent lock-bit not set and WP# = V
IH
or RP#
= V
HH
, block lock-bits can be cleared using the
Clear Block Lock-Bits command. If the permanent
lock-bit is set, clear block lock-bits operation is
unable. See
Table 5
for a summary of hardware
and software write protection options.
Clear block lock-bits option is executed by a two-
cycle command sequence. A clear block lock-bits
setup is first written. After the command is written,
the device automatically outputs status register data
when read (see
Fig. 8
). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bits
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to "1". Also, a reliable clear
block lock-bits operation can only occur when V
CC
=
V
CC1/2/3/4
and V
PP
= V
PPH1/2/3
. In a clear block lock-
bits operation is attempted while V
PP
≤
V
PPLK
, SR.3
and SR.5 will be set to "1". In the absence of this
high voltage, the block lock-bit contents are
protected against alteration. A successful clear block
lock-bits operation requires that the permanent lock-
bit is not set and WP# = V
IH
or RP# = V
HH
. If it is
attempted with the permanent lock-bit set or WP# =
V
IL
and RP# = V
IH
, SR.1 and SR.5 will be set to "1"
and the operation will fail. A clear block lock-bits
operation with V
IH
< RP# < V
HH
produce spurious
results and should not be attempted.
相關(guān)PDF資料
PDF描述
LH28F800SUT-70 8M (512K 】 16, 1M 】 8) Flash Memory
LH28F800BGR-BL12 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
LH28F800BGR-BL85 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
LH28F800BGR-TL12 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
LH28F800BGR-TL85 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LH28F800SG-L70 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memories
LH28F800SGN-L10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM
LH28F800SGN-L100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM
LH28F800SGN-L70 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM
LH28F800SGR-L10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM
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