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LH28F800SG-L/SGH-L (FOR TSOP, CSP)
1 INTRODUCTION
This datasheet contains LH28F800SG-L/SGH-L
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F800SG-L/
SGH-L flash memories documentation also includes
ordering information which is referenced in
Section 7.
1.1
Key enhancements of LH28F800SG-L/SGH-L
SmartVoltage flash memories are :
New Features
SmartVoltage Technology
Enhanced Suspend Capabilities
In-System Block Locking
Permanent Lock Capability,
Note following important differences :
V
PPLK
has been lowered to 1.5 V to support
3.3 V and 5 V block erase, word write, and lock-
bit configuration operations. Designs that switch
V
PP
off during read operations should make sure
that the V
PP
voltage transitions to GND.
To take advantage of SmartVoltage technology,
allow V
CC
connection to 2.7 V, 3.3 V or 5 V.
Once set the permanent lock bit, the blocks
which have been set block lock-bit can not be
erased, written forever.
1.2
The LH28F800SG-L/SGH-L are high-performance
8 M-bit SmartVoltage flash memories organized as
512 k-word of 16 bits. The 512 k-word of data is
arranged in sixteen 32 k-word blocks which are
individually erasable, lockable, and unlockable in-
system. The memory map is shown in
Fig. 1
.
Product Overview
SmartVoltage technology provides a choice of V
CC
and V
PP
combinations, as shown in
Table 1
, to
meet system performance and power expectations.
2.7 to 3.6 V V
CC
consumes approximately one-fifth
the power of 5 V V
CC
. But, 5 V V
CC
provides the
highest read performance. V
PP
at 2.7 V, 3.3 V and
5 V eliminates the need for a separate 12 V
converter, while V
PP
= 12 V maximizes block erase
and word write performance. In addition to flexible
erase and program voltages, the dedicated V
PP
pin
gives complete data protection when V
PP
≤
V
PPLK
.
Table 1 V
CC
and V
PP
Voltage Combinations
Offered by SmartVoltage Technology
Internal V
CC
and V
PP
detection circuitry auto-
matically configures the device for optimized read
and write operations.
A command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timing
necessary for block erase, word write, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (5 V
V
CC
, 12 V V
PP
) independent of other blocks. Each
block can be independently erased 100 000 times
(1.6 million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
Writing memory data is performed in word
increments typically within 7.5 μs (5 V V
CC
, 12 V
V
PP
). Word write suspend mode enables the
system to read data from, or write data to any other
flash memory array location.
V
CC
VOLTAGE
2.7 V
3.3 V
5 V
V
PP
VOLTAGE
2.7 V, 3.3 V, 5 V, 12 V
3.3 V, 5 V, 12 V
5 V, 12 V
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