參數(shù)資料
型號(hào)： LH7A405
英文描述： Microcontroller
中文描述： 微控制器
文件頁(yè)數(shù)： 21/53頁(yè)
文件大小： 396K
代理商： LH7A405
32-Bit System-on-Chip
LH7A405
Advance Data Sheet
21
LH7A405 BLUESTREAK JET
The LH7A405 BlueStreak JETprovides the following
features:
Bus interface allowing software to access JET registers
Bus interface allowing software to issue commands
to the JET
Bus interface allowing the JET to access system
memory
Memory management support for translating virtual
memory references
Input buffer for temporarily storing data requested
from memory
Output buffer for temporarily storing data being writ-
ten to memory
Global configuration registers for configuring com-
mon functionality
Global controls for acquiring and releasing accelera-
tion resources
Global controls for recognizing and handling context
switches
Global controls for synchronizing the Acceleration
Engine block
The BlueStreak JET offers a set of registers and
commands that software may use to interact with it.
Clock and State Controller
The clocking scheme in the LH7A405 is based
around two primary oscillator inputs. These are the
14.7456 MHz input crystal and the 32.768 kHz real time
clock oscillator; see Figure 3. The 14.7456 MHz oscil-
lator supplies the main system clock domains for the
LH7A405. The 32.768 kHz oscillator controls the
power-down operations and real time clock peripheral.
The clock and state controller provides the clock gating
and frequency division necessary, and then supplies
the clocks to the processor and rest of the system. The
amount of clock gating that actually takes place
depends on the power saving mode selected.
The 32.768 kHz clock provides the source for the
Real Time Clock tree and power-down logic. This clock
is used for the power state control and is the only clock
in the LH7A405 that runs continuously. The 32.768 kHz
clock is divided down to 1 Hz for the Real Time Clock
counter using a ripple divider to save power.
main system clocks for the LH7A405. It is the source
for PLL1 and PLL2, the primary clock for the peripher-
als, and the source clock to the programmable clock
(PGM) divider.
PLL1 provides the main clock tree for the chip. It gen-
erates the following clocks: FCLK, HCLK, and PCLK.
FCLK is the clock that drives the ARM922T core.
HCLK is the main bus (AHB) clock, as such it clocks
all memory interfaces, bus arbitrators and the AHB
peripherals. HCLK is generated by dividing FCLK by 1,
2, 3, or 4. HCLK can be gated by the system to enable
low power operation.
PCLK is the peripheral bus (APB) clock. It is gener-
ated by dividing HCLK by either 2, 4, or 8.
PLL2 generates a fixed 48 MHz clock signal for the
USB peripheral.
Power Modes
The LH7A405 has three operational states: Run,
Halt, and Standby. During Run all clocks are hardware
enabled and the processor is clocked. In the Halt mode
the device is functioning, but the processor clock is
halted while it waits for an event such as a key press.
Standby equates to the computer being switched ‘off’,
i.e. no display (LCD disabled) and the main oscillator is
shut down.
Reset Modes
Three external signals can generate resets to the
LH7A405: nPOR (power on reset), nPWRFL (power
failure) and nURESET (user reset). If any of these are
active, a system reset is internally generated. An nPOR
reset performs a full system reset. The nPWRFL and
nURESET resets perform a full system reset except for
the SDRAM refresh control, SDRAM Global Configura-
tion, SDRAM Device Configuration, and the RTC
peripheral registers. The SDRAM controller issues a
self-refresh command to external SDRAM before the
system enters an nPWRFL and nURESET reset. This
allows the system to maintain its Real Time Clock and
SDRAM contents. At reset termination, the chip enters
Standby mode. Once in the Run mode the PWRSR reg-
ister can be interrogated to determine the nature of the
reset and the trigger source, after which software can
then take appropriate actions.
相關(guān)PDF資料
PDF描述
LH8001 Microprocessor
LH8002 Microprocessor
LH8010 Peripheral IC
LH8030 Telecommunication IC
LH8036 Peripheral IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LH8000A-C 制造商:Black Box Corporation 功能描述:DUAL SPEED 10/100 STACKABLE HUB CLIENT
LH8000A-C-W1 制造商:Black Box Corporation 功能描述:1 YEAR WARRANTY FOR LH8000A-C
LH8000A-C-W3 制造商:Black Box Corporation 功能描述:3 YEAR WARRANTY FOR LH8000A-C
LH8000A-M 制造商:Black Box Corporation 功能描述:DUAL SPEED 10/100 STACKABLE HUB MASTER
LH8000A-M-SOL-W1 制造商:Black Box Corporation 功能描述:1 YEAR WARRANTY FOR LH8000A-M-SOL
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*