參數(shù)資料
型號(hào)： LH7A405
英文描述： Microcontroller
中文描述： 微控制器
文件頁(yè)數(shù)： 25/53頁(yè)
文件大?。?/td> 396K
代理商： LH7A405
32-Bit System-on-Chip
LH7A405
Advance Data Sheet
25
Vectored Interrupt Controller (VIC)
The LH7A405 VIC controls the interrupts of up to 32
different sources. Two VICs are daisy-chained together
to support up to 64 different interrupts. The VIC sup-
ports both FIQ and IRQ interrupts. FIQ interrupts have
a higher priority than IRQ interrupts. Each VIC can sup-
port up to 16 vectored interrupts, for a total of 32 vec-
tored interrupts. If two interrupts with the same priority
become active at the same time, the priority must be
resolved in software. When an interrupt becomes
active, the VIC generates an FIQ or IRQ if the corre-
sponding mask bit is set. No latching of interrupts takes
place in the VIC.
After a power-on reset, all mask register bits are
cleared, masking all interrupts. The mask bits must be
set by software after power-on reset for any interrupts
to be enabled.
A vectored interrupt has improved latency as it pro-
vides direct information about where its service routine
is located and eliminates software arbitration needed
with a simple interrupt controller.
The VICs continue to operate in Halt and Standby
modes, so external interrupts may bring the chip out of
these low power modes.
External Bus Interface
The ARM922T, LCD controller, and DMA engine
have access to an external memory system. The LCD
controller has access to an internal frame buffer in
embedded SRAM and an extension buffer in Synchro-
nous Memory for large displays. The processor and
DMA engine share the main system bus, providing
access to all external memory devices and the embed-
ded SRAM frame buffer.
An arbitration unit ensures that control over the
External Bus Interface (EBI) is only granted when an
existing access has been completed. See Figure 5.
Figure 5. External Bus Interface Block Diagram
ARM922T
LCD
CONTROLLER
EMBEDDED
SRAM
80KB
LCD AHB BUS
SYSTEM AHB BUS
LCD
MMU
DMA
CONTROLLER
ASYNCHRONOUS
MEMORY
CONTROLLER
BUS
ARBITER
SYNCHRONOUS
MEMORY
CONTROLLER
EXTERNAL
BUS
INTERFACE
(EBI)
A
SDRAM
SRAM
SDRAM
ROM
DATA
ADDRESS/
CONTROL
LH7A405-8
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