LH7A405
32-Bit System-on-Chip
6
Advance Data Sheet
AB2
PG4/nCFREG
GPIO Port G/Compact Flash Register memory access
8 mA
AA3
PG5/nCFCE1
GPIO Port G/Compact Flash Chip Enable 1
8 mA
AB3
PG6/nCFCE2
GPIO Port G/Compact Flash Chip Enable 2
8 mA
Y3
PG7/PCDIR
GPIO Port G/PC Card Direction
8 mA
AB4
PH0/CFRESETA
GPIO Port H/Compact Flash Reset A
8 mA
AA4
PH1/CFA8/CFA24/
CFRESETB
GPIO Port H/Compact Flash Address Bit 8/PCMCIA1 Address Bit 24/PCMCIA2 Reset B
8 mA
Y4
PH2/nCFENA
GPIO Port H/Compact Flash Enable A
8 mA
AB5
PH3/CFA9/CFA25/nCFENB GPIO Port H/Compact Flash Address Bit 9/PCMCIA1 Address Bit 25/PCMCIA2 Enable B
8 mA
AA5
PH4/nCFWAIT/nCFWAITA
GPIO Port H/Compact Flash WAIT Signal/PCMCIA WAIT A
8 mA
W5
PH5/CFA10/nCFWAITB
GPIO Port H/Compact Flash Address Bit 10/PCMCIA2 WAIT B
8 mA
AB6
PH6/AC97RESET
GPIO Port H/AC97 reset
8 mA
Y6
PH7/nCFSTATEN
GPIO Port H/Compact Flash Status Read Enable
8 mA
W6
LCDCLKIN
External Clock Input for LCD controller
AB7
nBLE2
Byte Lane Enable 2
16 mA
AA7
LCDVD0
LCD Video Data Interface
16 mA
Y7
LCDVD1
W7
LCDVD2
AB8
LCDVD3
AA8
PE0/LCDVD4
GPIO Port E and LCD Video Data Interface
16 mA
Y8
nBLE1
Byte Lane Enable 1
16 mA
P10
LCDM
AC bias for LCD. This signal is used on STN displays
16 mA
AB9
LCDDCLK
LCD Pixel Clock
16 mA
AA9
PE1/LCDVD5
GPIO Port E and LCD Video Data Interface
16 mA
Y9
PE2/LCDVD6
W9
PE3/LCDVD7
AB10 PD0/LCDVD8
GPIO Port D and LCD Video Data Interface
16 mA
AA10 PD1/LCDVD9
Y10
PD2/LCDVD10
W10
PD3/LCDVD11
AB11 PD4/LCDVD12
AA11 PD5/LCDVD13
Y11
PD6/LCDVD14
AB12 PD7/LCDVD15
AA12 BATCNTL
Battery Control for A/D controller battery monitor.
16 mA
N11
BOOTWIDTH0
Boot Width Pins. Used with the MEDCHG bit. On power up, the values on these pins are
latched to determine the width and type of Boot device. Boot width can be 8-, 16-, or 32-bit.
N12
BOOTWIDTH1
W12
LR_YM
Touch Screen Controller Lower Right Y-minus
AA13 AN1
A/D channel 1
Y13
AN6
A/D channel 6
W13
LL_YP
Touch Screen Controller Lower Left Y-plus
AB14 AN5
A/D channel 5
AA14 AN2
A/D channel 2
Y14
UR_XM
Touch Screen Controller Upper Right X-minus
Table 1. Functional Pin List (Cont’d)
BGA
SIGNAL
DESCRIPTION
OUTPUT
DRIVE