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參數(shù)資料
| 型號： | LH7A405 |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 35/53頁 |
| 文件大?。?/td> | 396K |
| 代理商： | LH7A405 |
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32-Bit System-on-Chip
LH7A405
Advance Data Sheet
35
AC Specifications (Commercial)
All signals described in Table 5 relate to transi-
tions following a reference clock signal. The illustra-
tion in Figure 6 represents all cases of these sets of
measurement parameters.
The reference clock signals in this design are:
HCLK, the System Bus internal clock
PCLK, the Peripheral Bus clock
SSPCLK, the Synchronous Serial Port clock
UARTCLK, the UART Interface clock
LCDDCLK, the LCD Data clock from the
LCD Controller
AC97CLK, the AC97 clock
SCLK, the Synchronous Memory clock.
All signal transitions are measured from the 50%
point of the clock to the 50% point of the signal.
For outputs from the LH7A405, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from the rising edge of the reference clock signal.
Maximum requirements for tOVXXX are shown in
Table 5.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid following
the rising edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 5.
For inputs, tISXXX (e.g. tISD) represents the
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 5.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid following
the rising edge of the reference clock signal. Minimum
requirements are shown in Table 5.
Figure 6. LH7A405 Signal Timing
Table 5. AC Signal Characteristics
SIGNAL
TYPE
LOAD
DRIVE
SYMBOL
MIN.
MAX.
DESCRIPTION
ASYNCHRONOUS MEMORY INTERFACE SIGNALS
tOVA
tOHA
tOVD
tOHD
tISD
tIHD
tOVCS
tOHCS
tOVWE
tOHWE
tOVBLE
tOHBLE
tOVOE
tOHOE
A[27:0]
Output
50 pF
8 mA
8 ns
Address Valid
Address Hold
Data Valid
Data Hold
Data Setup
Data Hold
Chip Select Valid
Chip Select Hold
Write Enable Valid
Write Enable Hold
Byte Lane Enable Valid
Byte Lane Enable Hold
Ouput Enable Valid
Ouput Enable Hold
0 ns
D[31:0]
Output
50 pF
8 mA
6 ns
2 ns
2 ns
0 ns
Input
nCS[7:0]
Output
30 pF
8 mA
8 ns
0 ns
nWE[3:0]
Output
30 pF
8 mA
8 ns
0 ns
nBLE[3:0]
Output
30 pF
8 mA
8 ns
0 ns
nOE
Output
30 pF
8 mA
8 ns
0 ns
REFERENCE
CLOCK
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
tOVXXX
tOHXXX
tISXXX tIHXXX
LH7A405-9
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| LH8000A-C | 制造商:Black Box Corporation 功能描述:DUAL SPEED 10/100 STACKABLE HUB CLIENT |
| LH8000A-C-W1 | 制造商:Black Box Corporation 功能描述:1 YEAR WARRANTY FOR LH8000A-C |
| LH8000A-C-W3 | 制造商:Black Box Corporation 功能描述:3 YEAR WARRANTY FOR LH8000A-C |
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