參數(shù)資料
型號(hào)： LXT6155
廠商： Intel Corp.
英文描述： 155 Mbps SDH/SONET/ATM Transceiver
中文描述： 155速率的SDH / SONET / ATM的收發(fā)器
文件頁(yè)數(shù)： 18/50頁(yè)
文件大?。?/td> 291K
代理商： LXT6155
LXT6155 — 155 Mbps SDH/SONET/ATM Transceiver
18
Datasheet
2.3
Clocks
2.3.1
Parallel Mode
The LXT6155 accepts TPICLK synchronized with transmit input parallel data TPID<7:0>. The
data is serialized and transmitted at TTIP0/TRING0 or TTIP1/TRING1 depending on which line
encoding mode is selected. The LXT6155 in turn produces the receive output parallel clock
RPOCLK, that is recovered from incoming line data RTIP/RRING, and is synchronized with
receive output parallel data RPOD<7:0>.
2.3.1.1
Transmit Parallel Input Clock (TPICLK)
TPICLK is the transmit parallel input clock provided by the systems interface. This clock must be
nominally 19.44 MHz, synchronized with parallel input data TPID<7:0>. This clock is then
internally multiplied by 8 to produce a serial clock, used for parallel-to-serial conversion, line
drivers, and pulse reshaping. In HW mode (HWSEL = Low), TPID data is sampled on the falling
edge of TPICLK. In SW mode (HWSEL = High), the clock polarity can be inverted (Reg #0, bit
#3).
2.3.1.2
Receive Parallel Output Clock (RPOCLK)
RPOCLK is the parallel output clock that is recovered from the line input data RTIP/RRING. This
clock is at 19.44 MHz, synchronized with parallel output data RP0D<7:0>. In HW mode (HWSEL
= Low), the RPOCLK clock rising edge is at the center of eye opening of RPOD<7:0> as shown in
Figure 21. In SW mode (HWSEL = High), the clock polarity can be inverted (Reg #0, bit #2).
Under LOS (LOS=High) or Rx PLL loss of lock (LOCK=Low) conditions RPOCLK is switched to
the reference selected by the CIS control in HW mode, or Reg #0 bit #5 in SW mode. Also, the
parallel output is forced to all zeros. This feature can be disabled in SW mode (HWSEL = High)
via register #10, bit #7.
2.3.2
Serial Mode
At the transmit systems interface, the LXT6155 accepts the transmit input clock TSICLKP/
TSICLKN that is synchronized to incoming serial differential data TPOS/TNEG. At the line
interface, the LXT6155 accepts RTIP/RRING data and produces the clocks RSOCLKP/
RSOCLKN synchronized to receive output data RPOS/RNEG. RSOCLKP/RSOCLKN clock edges
are at the center of RPOS/RNEG.
2.3.2.1
Transmit Serial Input Clock (TSICLKP/TSICLKN)
TSICLKP/TSICLKN is the serial input clock from the overhead terminator. This 155.52 MHz
clock is rising edge centered with input serial data on TPOS and TNEG. These clock pins should be
left open when the LXT6155 operates in parallel mode.
2.3.2.2
Receive Serial Output Clock (RSOCLKP/RSOCLKN)
RSOCLKP/RSOCLKN is the serial clock recovered from the line input data on RTIP/RRING. This
155.52 MHz clock is falling edge centered with receive serial output data on RPOS/RNEG. These
clock pins should be left open when the LXT6155 operates in parallel mode. Under LOS
相關(guān)PDF資料
PDF描述
LXT6234 E-Rate Multiplexer
LXT901 8QLYHUVDO (WKHUQHW 7UDQVFHLYHU
LXT901A 8QLYHUVDO (WKHUQHW 7UDQVFHLYHU
LXT907A 8QLYHUVDO (WKHUQHW 7UDQVFHLYHU
LXT902 Ethernet Twisted-Pair Media Attachment Unit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT6155LE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm
LXT6234 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:E-Rate Multiplexer
LXT6251A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC
LXT901 制造商:LVL1 制造商全稱:LVL1 功能描述:8QLYHUVDO (WKHUQHW 7UDQVFHLYHU
LXT901/LXT907 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LXT901. LXT907 - Design Guide for LXT901/907 Ethernet Interface Connection to Motorola MC68EN360 Controller
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*