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參數(shù)資料
| 型號： | LXT6155 |
| 廠商： | Intel Corp. |
| 英文描述： | 155 Mbps SDH/SONET/ATM Transceiver |
| 中文描述： | 155速率的SDH / SONET / ATM的收發(fā)器 |
| 文件頁數(shù)： | 31/50頁 |
| 文件大?。?/td> | 291K |
| 代理商： | LXT6155 |
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Datasheet
31
155 Mbps SDH/SONET/ATM Transceiver — LXT6155
.
.
5:4
1.1
los_ena
LOS disable controls (amplitude LOS & digital LOS):
0 = disable
1 = enable
3
0
frame_ena
Byte align enable: If used, this feature must be enabled during system
configuration prior to applying data to the receiver. If this is not possible see
application note AN141 for further details.
0 = byte align disabled
1 = byte align enabled
2
0
Not for customer use
1
0
Not for customer use
0
1
Not for customer use
Table 20. Rx Digital 1, Register #12 (Address A<3:0>=1100) (Continued)
Bit
Default
Mnemonic
Description
Figure 15. Rx Digital 2, Register #13 (Address A<3:0>=11001)
Bit
Default
Mnemonic
Description
7
1
rx_dig_reset
Rx digital circuitry reset. This can be used to minimize power comsumption when
the device is disabled but not powered down. It must be enabled when the device
is active
0 = reset
1 = normal operation
6:3
0.0.0.0
cnffp
Frame pulse position. Refer to figure 5 for usage.
2:1
1.0
los_tran_assert
D-LOS transition density count for assertion:
00 = 128
01 = 512
10 = 3112
11 = 4096
A-LOS assertion integration period:
00 = 2048 bits
01 = 512 bits
10 = 128 bits
11 = 32 bits
0
1
los_tran_deassert
D-LOS transition density count for de-assertion:
0 = 4/32
1 = SONET compliant
1
A-LOS de-assertion integration period:
0 = 0 bits
1 = 128 bits
1. SONET compliant LOS de-assertion refers to Bellcore GR-253, pages 6-16 (section 6.2.1.1.1), recommendation R6-54, LOS alarm is de-asserted
(cleared) when two valid frame headers have been received with no LOS events in the interval.
Table 21. Status Control, Register #14 (Address A<3:0>=1110)
Bit
Default
Mnemonic
Description
7:4
0.0.0.0
-
Unused
3:0
0.0.0.0
stat_cont
Status register (register #15) mux control (indirect addressing to increase read
space)
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