參數(shù)資料
型號(hào)： LXT6155
廠商： Intel Corp.
英文描述： 155 Mbps SDH/SONET/ATM Transceiver
中文描述： 155速率的SDH / SONET / ATM的收發(fā)器
文件頁(yè)數(shù)： 27/50頁(yè)
文件大?。?/td> 291K
代理商： LXT6155
Datasheet
27
155 Mbps SDH/SONET/ATM Transceiver — LXT6155
.
Table 8.
Primary Control Register Settings, Register #0 (Address A<3:0>=0000)
Bit
Default
Mnemonic
Description
7
0
lpbk_cntl
Local loopback:
0 = No loopback
1 = Activate local loopback
6
0
Remote loopback:
0 = No loopback
1 = Activate remote loopback
5
0
pll_ref
PLL/Equalizer reference clock control:
0 = Use TPICLK clock
1 = Use external crystal (XTALIN)
4
0
-
Not used
3
1
clk_inv
T
PICLK
polarity at system interface:
0 = TPID <7:0> sampled on the rising edge of TPICLK
1 = TPID <7:0> sampled on the falling edge of TPICLK
2
1
R
POCLK
polarity at system interface:
0 = RPOD <7:0> transitions on the rising edge of RPOCLK
1 = RPOD <7:0> transitions on the falling edge of RPOCLK
1
0
sys_int
Systems interface mode selection:
0 = Serial mode
1 = Parallel 8 bit mode
0
0
media_sel
Media and line code selection:
0 = Fiber (NRZ)
1 = Coax (CMI)
Table 9.
Tx Control, Register #1 (Address A<3:0>=0001)
Bit
Default
Mnemonic
Description
7
1
tx_ena
Tx output enable:
0 = outputs disabled
1 = outputs active
6
1
tx_dig_reset
Tx digital circuitry reset. This can be used to minimize power comsumption when
the device is disabled but not powered down. It must be enabled when the device
is active.
0 = reset
1 = active
5
0
4:1
0.1.1.1
tx_amp_trim
Transmit amplitude trim:
0000 = -21%
1111 = +24%
0
1
tx_clk_sw_ena
Tx clock detection enable. This must be disabled in SW mode when pll_ref=0
(reg#0<5>=0)
0 = disable
1 = enable
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