參數(shù)資料
型號(hào)： LXT6155
廠商： Intel Corp.
英文描述： 155 Mbps SDH/SONET/ATM Transceiver
中文描述： 155速率的SDH / SONET / ATM的收發(fā)器
文件頁(yè)數(shù)： 22/50頁(yè)
文件大?。?/td> 291K
代理商： LXT6155
LXT6155 — 155 Mbps SDH/SONET/ATM Transceiver
22
Datasheet
2.5.2
Software Mode
When HWSEL = High, the LXT6155 operates in Software Mode. Control is through an external
serial
μ
P interface. Figure 8 shows the pins used in Software Mode. The LXT6155 uses four pins
for the industry standard Serial Control Interface (SCP) bus: SCLK, CS, SDI and SDO. SCLK is
the serial input control clock pin. CS is the chip select input. SDI is the serial data input pin, and
SDO is the serial data output pin. Figures 9 and 10 show the serial interface data structure. A data
transaction is initiated by a falling edge on the Chip Select pin CS. A High-to-Low transition on CS
is required for each access to the control registers. The first bit is a read/write bit (R/W), followed
by seven address bits (A<6:0>), and eight data bits (D<7:0>). Every data transaction requires 16
SCLK cycles to complete. If R/W = High (Read), the LXT6155 outputs a data byte D<7:0> on the
SDO pin. If R/W = Low (Write), the LXT6155 accepts a data byte D<7:0> on the SDI pin, while
tristating SDO pin.
It is recommended in SW mode operation, the registers are first initialized by writing a “0” to
register #11 bit #6 (reset).
2.5.2.1
Serial Input Clock (SCLK)
This pin accepts a clock up to 4.096 MHz for data transactions between the LXT6155 and the SCP
bus. The LXT6155 clocks SDO data out on the falling edge, and clocks SDI data in on the rising
edge of SCLK (see Figures 9 and 10).
2.5.2.2
Chip Select Input (CS)
On the falling edge of CS, the LXT6155 starts data transactions. On the rising edge of CS, the
LXT6155 stops data transaction. The CS pin must be held Low for at least 16 SCLK cycles to
complete a full Read or Write data transaction. If CS is held Low less than 16 SCLK cycles, then
the data transaction is ignored. At the end of each Write/Read transaction, CS must return High,
between the 16th and 17th clock edges.
2.5.2.3
Serial Input Word (SDI)
Figure 10 shows the serial interface input data word structure. When the first input bit R/W = Low,
a Write operation is performed. The SCLK clocks data in on the SDI pin during the second 8 bits
D<7:0> of the Write operation. Data is clocked in on the rising edge of SCLK. During the entire 16
bit operation, SDO remains tristated. Refer to Tables 6 through 22 for control register descriptions.
2.5.2.4
Serial Output Word (SDO)
The serial output word structure is shown in Figure 9. When the first input bit R/W = High, a Read
operation is specified. SDO becomes active after A0 has been clocked in. The first bit out of SDO
changes the state of SDO from High-Z to a Low/High. SDO is clocked out on the falling edge of
SCLK.
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