參數(shù)資料
型號(hào): M12L64322A-7BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 512K x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA90
封裝: 8 X 13 MM, LEAD FREE, BGA-90
文件頁(yè)數(shù): 26/47頁(yè)
文件大小: 791K
代理商: M12L64322A-7BG
ES MT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision
:
2.3
26/47
12. About Burst Type Control
Sequential Counting
Interleave Counting
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
Basic
MODE
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Random
MODE
Random Column Access
t
CCD
= 1 CLK
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
1
At MRS A210 = “000”
At auto precharge . tRAS should not be violated.
2
At MRS A210 = “001”
At auto precharge . tRAS should not be violated.
4
At MRS A210 = “010”
8
At MRS A210 = “011”
Basic
MODE
Full Page
At MRS A210 = “111”
At the end of the burst length , burst is warp-around.
Random
MODE
Burst Stop
t
BDL
= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Using burst stop command, any burst length control is possible.
RAS Interrupt
(Interrupted by
Precharge)
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
t
RDL
= 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Interrupt
MODE
CAS Interrupt
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
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