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參數(shù)資料
| 型號： | M12L64322A-7TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
| 封裝： | 0.400 X 0.875 INCH, 0.50 MM PITCH, LEAD FREE, TSOP2-86 |
| 文件頁數(shù)： | 4/47頁 |
| 文件大?。?/td> | 791K |
| 代理商： | M12L64322A-7TG |
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ES MT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision
:
2.3
4/47
DQM0~3
DQ
Mode
Register
C
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
R
Bank A
Bank B
Sense Amplifier
Column Decoder
Data Control Circuit
L
I
B
Address
Clock
Generator
CLK
CKE
C
CS
RAS
CAS
WE
BLOCK DIAGRAM
PIN DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and DQM0-3.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A10
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
BA0 , BA1
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12S128168A | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12S128168A-10TG | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12S16161A-7BG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12S16161A-7TG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12S64322A | 512K x 32 Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L64322A-7TG2U | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks |
| M-12-LID-PLATED | 功能描述:罩類、盒類及殼類產(chǎn)品 PLTD LID FOR M12 RoHS:否 制造商:Bud Industries 產(chǎn)品:Boxes 外部深度:6.35 mm 外部寬度:6.35 mm 外部高度:2.56 mm NEMA 額定值: IP 等級: 材料:Acrylonitrile Butadiene Styrene (ABS) 顏色:Red |
| M12M1 | 制造商:TE Connectivity 功能描述: |
| M12M124D-0.5 | 制造商:L COM 功能描述:CA M12 TO M12 4 POS D .5M |
| M12M124D-1 | 制造商:L COM 功能描述:CA M12 TO M12 4 POS D 1M |
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