參數(shù)資料
型號(hào)： M12L64322A-7TG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 512K x 32 Bit x 4 Banks Synchronous DRAM
中文描述： 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86
封裝： 0.400 X 0.875 INCH, 0.50 MM PITCH, LEAD FREE, TSOP2-86
文件頁(yè)數(shù)： 43/47頁(yè)
文件大?。?/td> 791K
代理商： M12L64322A-7TG
ES MT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision
:
2.3
43/47
Self Refresh Entry & Exit Cycle
*Note :
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
RC
is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
BA 0, BA 1
S el f R ef r es h E n t r y
A u t o R ef r es h
: D o n ' t c a r e
*Not e 2
*Not e 1
t
S S
*No t e 3
*Not e 4
t
R C
m i n
*Not e 6
S e l f R ef r e s h E xi t
H i - Z
H i - Z
*No t e 5
*Not e 7
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
相關(guān)PDF資料
PDF描述
M12S128168A 2M x 16 Bit x 4 Banks Synchronous DRAM
M12S128168A-10TG 2M x 16 Bit x 4 Banks Synchronous DRAM
M12S16161A-7BG 512K x 16Bit x 2Banks Synchronous DRAM
M12S16161A-7TG 512K x 16Bit x 2Banks Synchronous DRAM
M12S64322A 512K x 32 Bit x 4 Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M12L64322A-7TG2U 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks
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M12M124D-1 制造商:L COM 功能描述:CA M12 TO M12 4 POS D 1M
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