- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377801 > M13S64164A-6BG (ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC) 1M x 16 Bit x 4 Banks Double Data Rate SDRAM PDF資料下載
參數(shù)資料
| 型號： | M13S64164A-6BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| 中文描述： | 4M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封裝： | 13 X 8 MM, LEAD FREE, BGA-60 |
| 文件頁數(shù)： | 18/49頁 |
| 文件大?。?/td> | 1526K |
| 代理商： | M13S64164A-6BG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
ES MT
Preliminary
M13S64164A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 0.3 18/49
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
<Burst Length = 4,
CAS
Latency = 3>
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) clocks
［
RU mean round up to the nearest integer
］
before
the Write command.
<Burst Length = 4,
CAS
Latency = 3>
t
CCD
C A S L at e n c y= 3
0
1
2
3
4
5
6
7
8
CO M M AN D
DQS
DQ 's
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Dout A
0
READ B
Dout A
1
Dout B
2
Dout B
3
Dout B
0
Dout B
1
C L K
C L K
C A S L at e n c y= 3
0
1
2
3
4
5
6
7
8
CO MM AN D
DQS
DQ 's
READ
NOP
W RITE
NOP
NOP
NOP
NOP
NOP
Dout 0
Burst Stop
Din 0
Dout 1
Din 1 Din 2
Din 3
C L K
C L K
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M13S64164A | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64164A-5BG | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64164A-5TG | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64164A-6TG | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M14256 | Memory Card IC 256K Bit Serial IIC Bus EEPROM(256K位串行IIC總線EEPROM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M13S64164A-6BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64164A-6TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64164A-6TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64322A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM |
| M-14 | 功能描述:TERM BARRIER 14CIRC DUAL ROW RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:M 標準包裝:10 系列:Beau™ 38780 端接塊類型:阻隔塊 電路數(shù):15 導線入口數(shù)目:30 間距:0.438"（11.12mm） 行數(shù):2 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘 底部端子:焊片 阻擋層類型:雙壁（雙） 特點:法蘭 顏色:黑 包裝:散裝 安裝類型:通孔 工作溫度:- 材料 - 絕緣體:聚對苯二甲酸丁二酯（PBT），玻璃纖維增強型 材料可燃性額定值:UL94 V-0 其它名稱:038780-111538780-1115387801115 |
發(fā)布緊急采購，3分鐘左右您將得到回復。