參數(shù)資料
型號: M13S64164A-6BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
中文描述: 4M X 16 DDR DRAM, 0.7 ns, PBGA60
封裝: 13 X 8 MM, LEAD FREE, BGA-60
文件頁數(shù): 26/49頁
文件大?。?/td> 1526K
代理商: M13S64164A-6BG
ES MT
Preliminary
M13S64164A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 0.3 26/49
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping t
WR
(min).
<Burst Length = 4>
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and
WE
high at the rising edge of
the clock(CLK). All banks must be precharged and idle for t
RP
(min) before the auto refresh command is applied. No control of the
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the t
RFC
(min).
A maximum of eight consecutive AUTO REFRSH commands (with tRFCmin) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6
μ
m.
0
1
2
3
4
5
6
7
8
CO MM AN D
DQS
DQ 's
B a n k A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Dout 0 Dout 1
Write A
Auto Precharge
Dout 2 Dout 3
*B a n k c an b e r e ac t iv at e d a t
c om p l e t io n o f
t
R P
t
W R
t
R P
In t e r n al p r e c h ar g e s t a r t
C L K
C L K
CO M M AN D
CKE = High
t
R P
PRE
RAuto
C M D
t
R F C
C L K
C L K
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