DMAC
100
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
DMAi control register
(i=0,1)
Symbol
DM0CON
DM1CON
Address
002C
16
003C
16
After reset
00000X00
2
00000X00
2
Bit name
Function
Bit symbol
Transfer unit bit select bit
b7
b6
b5
b4
b3
b2
b1
b0
0 : 16 bits
1 : 8 bits
DMBIT
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMA request bit
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 2)
Destination address
direction select bit (Note 2)
0 : Fixed
1 : Forward
DSD
DAD
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
Note 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
Note 2: At least one of the DAD and DSD bits must be “0” (address direction fixed).
(Note 1)
DMA1 request cause select register
Symbol
DM1SL
Address
03BA
16
After reset
00
16
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
DMA request cause
select bit
DSEL0
RW
DSEL1
DSEL2
DSEL3
Software DMA
request bit
DSR
DSEL3 to DSEL0
0 0 0 0
2
0 0 0 1
2
0 0 1 0
2
0 0 1 1
2
0 1 0 0
2
0 1 0 1
2
0 1 1 0
2
0 1 1 1
2
1 0 0 0
2
1 0 0 1
2
1 0 1 0
2
1 0 1 1
2
1 1 0 0
2
1 1 0 1
2
1 1 1 0
2
1 1 1 1
2
DMS=0(basic cause of request)
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive/ACK0
UART2 transmit
UART2 receive/ACK2
A-D conversion
UART1 receive/ACK1
DMS=1(extended cause of request)
–
–
–
–
–
SI/O3
SI/O4
Two edges of INT1
–
–
–
–
–
–
–
–
Bit name
DMA request cause
expansion select bit
DMS
RW
RW
RW
RW
RW
RW
(b5-b4)
RW
RW
RW
RW
RW
RW
RW
(b7-b6)
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “0001
2
”
(software trigger).
The value of this bit when read is “0” .
0: Basic cause of request
1: Extended cause of request
Refer to note
Figure 1.13.3. DM1SL Register, DM0CON Register, and DM1CON Registers