Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
146
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
UARTi special mode register 2 (i=0 to 2)
Symbol
Address
After reset
X0000000
2
U0SMR2 to U2SMR2 036E
16
, 0372
16
, 0376
16
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
RW
Function
STAC
SWC2
SDHI
I C mode select bit 2
SCL wait output bit
0 : Disabled
1 : Enabled
SDA output stop bit
UARTi initialization bit
Clock-synchronous bit
Refer to Table 1.20.4
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ALS
0 : Disabled
1 : Enabled
SDA output disable bit
SCL wait output bit 2
0: Enabled
1: Disabled (high impedance)
0 : Disabled
1 : Enabled
0: Transfer clock
1: 0 output
UARTi special mode register 3 (i=0 to 2)
Symbol
Address
After reset
000X0X0X
2
U0SMR3 to U2SMR3
036D
16
, 0371
16
, 0375
16
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
Function
DL2
SDAi digital delay
setup bit
(Note 1, Note 2)
DL0
DL1
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
0 : Without clock delay
1 : With clock delay
b7 b6 b5
Nothing is assigned. When write, set “0”. When read, its content is
indeterminate.
Clock phase set bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
Clock output select bit
CKPH
NODC
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I
2
C mode. In other than I
2
C
mode, set these bits to “000
2
” (no delay).
Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
RW
RW
RW
RW
RW
RW
RW
(b7)
RW
RW
RW
RW
RW
RW
(b0)
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b2)
(b4)
Figure 1.17.7. U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers