Programmable I/O Ports
217
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Port Pi register (i=0 to 7 and 9 to 13) (Note 2, 3)
Symbol
P0 to P3
P4 to P7
P9 to P12
P13
Bit symbol
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Address
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
03E0
16
, 03E1
16
, 03E4
16
, 03E5
16
03E8
16
, 03E9
16
, 03EC
16
, 03ED
16
03F1
16
, 03F4
16
,
03F5
16
, 03F8
16
03F9
16
Bit name
Port Pi
0
bit
Port Pi
1
bit
Port Pi
2
bit
Port Pi
3
bit
Port Pi
4
bit
RW
RW
RW
RW
RW
RW
RW
RW
RW
b7
b6
b5
b4
b3
b2
b1
b0
Pi_5
Pi_6
Pi_7
Port Pi
5
bit
Port Pi
6
bit
Port Pi
7
bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : “L” level
1 : “H” level (Note 1)
(i = 0 to 7 and 9 to 13)
Port P8 register
Symbol
P8
Address
03F0
16
After reset
Indeterminate
Bit name
Function
Bit symbol
P8_0
b7
b6
b5
b4
b3
b2
b1
b0
Port P8
0
bit
P8_1
Port P8
1
bit
P8_2
Port P8
2
bit
P8_3
Port P8
3
bit
P8_4
Port P8
4
bit
P8_5
Port P8
5
bit
P8_6
Port P8
6
bit
P8_7
Port P8
7
bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register (except for P8
5
)
0 : “L” level
1 : “H” level
Note 1: Since P7
0
and P7
1
are N-channel open drain ports, the data is high-impedance.
Note 2: During memory extension and microprocessor modes, the Pi register for the pins
functioning as bus control pins (A
0
to A
19
, D
0
to D
15
, CS
0
to CS
3
, RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
Note 3: To use ports P11 to P14, set the PUR3 register’s PU37 bit to “1” (enable). If this bit is set to
“0” (disable), the P11 to P14 registers are cleared to ‘00
16
’ and the P11 to P14 pins are
placed in the high-impedance state.
RW
RW
RW
RW
RW
RW
RO
RW
RW
Figure 1.25.8. P0 to P13 Registers