6
1.1 Precautions for Interrupts
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
1.1.6 Rewrite the Interrupt Control Register
Each interrupt control register can only be modified while no interrupt requests corresponding to that
register are generated. If interrupt requests managed by any interrupt control register are likely to occur,
disable the interrupts before modifying the register. A sample program is shown below.
To modify any interrupt control register after disabling interrupts, be careful with the instructions used.
(1) Modifying Other Than the IR Bit
If an interrupt request corresponding to that register is generated while executing the instruction, the IR
bit may not be set to
“
1
”
(= interrupt requested), with the result that the interrupt request is ignored. If this
presents a problem, use the following instructions to modify the register.
Instructions to use: AND, OR, BCLR, BSET
(2) Modifying the IR Bit
Even when the IR bit is cleared to
“
0
”
(= interrupt not requested), it may not actually be cleared to
“
0
”
depending on the instruction used. Therefore, use the MOV instruction to clear the IR bit.
Example 1:
INT_SWITCH1:
FCLR
AND.B
NOP
NOP
FSET
I
#00h, 0055h
; Disable interrupts.
; Set the TA0IC register to
“
00
16
”
.
;
Four NOP instructions are required when using HOLD function.
I
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
AND.B
MOV.W MEM, R0
FSET
I
#00h, 0055h
; Disable interrupts.
; Set the TA0IC register to
“
00
16
”
.
; Dummy read.
; Enable interrupts.
I
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
AND.B
POPC
; Push Flag register onto stack
; Disable interrupts.
; Set the TA0IC register to
“
00
16
”
.
; Enable interrupts.
I
#00h, 0055h
FLG
Why the FSET I instruction is preceded by two NOP instructions (four when using HOLD function) in
Example 1 and why the FSET I instruction is preceded by a dummy read in Example 2
This is to prevent the I flag from being set to
“
1
”
before writing to the interrupt control register for reasons
of the instruction queue buffer.