Reset
27
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Power Supply Down Detection Interrupt
A power supply down detection interrupt request is generated when the input voltage at the V
CC1
pin rises
to Vdet4 or more or drops below Vdet4 while the D40 bit in the D4INT register is set to “1” (power supply
down detection interrupt enable). The power supply down detection interrupt shares the interrupt vector
with the watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
To use the power supply down detection interrupt to get out of stop mode, set the D41 bit in the D4INT
register to “1” (enable).
The D42 bit in the D4INT register becomes “1” when passing through Vdet4 is detected after the voltage
inputted to the V
CC1
pin is up or down.
A power supply down detection interrupt is generated when the D42 bit changes state from “0” to “1”. The
D42 bit needs to be set to “0” in a program. However, where the D41 bit is “1” and the stop mode is selected,
the power supply down detection interrupt request arises, and the microcomputer is reset from the stop
mode with no regard for the status of D42 bit if it is detected that the voltage applied to the V
CC1
pin has
increased, passing through Vdet4.
Table 1.5.2 shows the power supply down detection interrupt request generation conditions.
It is possible to set the sampling clock detecting that the voltage applied to the V
CC1
pin has passed through
Vdet4 with the DF1 to DF0 bits of D4INT register. Table 1.5.3 shows sampling clock periods.
Table 1.5.2. Power Supply Down Detection Interrupt Request Generation Conditions
Bit, Vdet4 passing detection, operation mode condition
VC27
bit
Generated
From 1 to 1
(No change)
Not detected
Note 1: The status except the wait mode and stop mode is handled as the normal mode.(Refer to “Clock generating circuit”)
Note 2: Refer to “Limitations on stop mode”, “Limitations on wait mode”.
D40
bit
Vdet4 passing
detection
D42 bit
D41
bit
VC13
bit
Operation mode
(Notes 1, 2)
Power supply
down detection
Interrupt
request
0
1
Not generated
0
1
Detected
From 0 to 1
0
Normal, wait
Stop
Not generated
1
Generated
0
Not generated
1
From 0 to 1
(Up)
Normal, wait
Stop
Generated
From 1 to 0
(Down)
Not generated
Table 1.5.3. Sampling Clock Periods
CPU
clock
(MHz)
divided by 8 divided by 16
16
1.5
3.0
divided by 32
divided by 64
Sampling clock (μs)
6.0
12.0
Precautions
1. Limitations on Stop Mode
If the CM10 bit in the CM1 register is set to “1” (stop mode) when the VC13 bit in the VCR1 register is “1”
(V
CC1
≥
Vdet4) while the VC27 bit in the VCR2 register is “1” (power supply down detection circuit enable)
and the D40 bit in the D4INT register is “1” (power supply down detection interrupt enable) and D41 bit in
the D4INT register is “1” (power supply down detection interrupt is used to get out of stop mode), a power
supply down detection interrupt is immediately generated, causing the microcomputer to exit stop mode.
In systems where the microcomputer enters stop mode when the input voltage at the V
CC1
pin drops
below Vdet4 and exits stop mode when the input voltage rises to Vdet4 or more, make sure the CM10 bit
is set to “1” when VC13 bit is “0” (V
CC1
< Vdet4).