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Serial I/O2
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Serial I/O2 Mode
There are two types of serial I/O2 modes: 8-bit serial I/O mode where automatic transfer RAM is not
used, and an automatic transfer serial I/O mode.
(1) 8-bit Serial I/O Mode
Address 0346
16
is assigned to the serial I/O2 register. When the internal synchronous clock is
selected, a serial transfer of the 8-bit serial I/O is started by a write signal to the serial I/O2 register
(address 0346
16
).
The serial transfer status flag (bit 5 of address 0344
16
) is set to “1” by writing into the serial I/O2
register and reset to “0” after completion of 8-bit transfer. At the same time, a serial I/O2 interrupt
request occurs. If the transfer is completed, the receive data is read out from serial I/O2 register.
When the external synchronous clock is selected, the contents of the serial I/O2 register are con-
tinuously shifted while transfer clocks are input to S
CLK21
or S
CLK22
. Therefore, the clock needs to
be controlled externally.
(2) Automatic Transfer Serial I/O Mode
Address 0346
16
is assigned to the transfer counter (1-byte units). The serial I/O2 automatic trans-
fer controller controls the write and read operations of the serial I/O2 register. The serial I/O auto-
matic transfer RAM is mapped to addresses 00400
16
to 004FF
16
. Before starting transfer, make
sure the 8 low-order bits of the address that contains the beginning data to be serially transferred is
set to the automatic transfer data pointer (address 0340
16
).
When the internal synchronous clock is selected, the transfer interval is inserted between one data
and another in the following cases:
1. When using no handshake signal
2. When using the S
RDY2
output, S
BUSY2
output, and S
STB2
output of the handshake signal inde
pendently
3. When using a combination of S
RDY2
output and S
STB2
output or a combination of S
BUSY2
output
and S
STB2
output of the handshake signal
The transfer interval can be set in the range of 2 to 23 cycles using the automatic transfer interval
set bit (bits 0–4 of address 0348
16
).
Also, when using S
BUSY2
output as a signal for each occurrence of the all transfer data, a transfer
interval is inserted before the system starts sending or receiving the first data and after the system
finished sending or receiving the last data, not just between one data and another.
Furthermore, when using S
STB2
output, the transfer interval between each 1-byte data is extended
by 2 cycles from the set value no matter how the S
BUSY2
output. S
STB2
output function select bit (bit
4 of address 0344
16
) is set.
When using S
BUSY2
output and S
STB2
output in combination as a signal for each occurrence of the
all transfer data, the transfer interval after the system finished sending or receiving the last data is
extended by 2 cycles from the set value.
When an external synchronous clock is selected, the automatic transfer interval is disabled.