
48
DMAC
M
i
t
s
u
M
S
b
i
s
3
M
h
0
I
C
i
m
2
R
i
1
O
c
r
8
C
o
c
o
G
M
m
p
r
P
u
t
u
T
e
r
p
R
s
o
U
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
O
E
Figure 34. Block diagram of DMAC
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-
bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 34 shows the block diagram of the
DMAC. Table 12 shows the DMAC specifications. Figure 35 to Figure 36 show the registers used by the
DMAC.
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAAAA
AAAAAAA
AAAAAA
Data bus low-order bits
DMA latch high-order bits
DMA latch low-order bits
AA
AA
DMA0 forward address pointer (20) (Note)
AA
Data bus high-order bits
A
A
A
AAAAAAAAAAAAAAAAAAAAAAAA
Address bus
AA
AA
AA
DMA1 forward address pointer (20) (Note)
AA
AA
AA
DMA0 transfer counter TCR0 (16)
AA
AA
DMA1 transfer counter TCR1 (16)
(addresses 0029
16
, 0028
16
)
16
, 0038
16
)
(addresses 0022
16
to 0020
16
)
16
to 0024
16
)
(addresses 0032
16
to 0030
16
)
16
to 0034
16
)
Note: Pointer is incremented by a DMA request.
AA
A