22
Clock Generating Circuit
M
i
t
s
u
M
S
b
i
s
3
M
h
0
I
C
i
m
2
R
i
1
O
c
r
8
C
o
c
o
G
M
m
p
r
P
u
t
u
T
e
r
p
R
s
o
U
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
O
E
Figure 18 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
Symbol
CM0
Address
16
When reset
48
16
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
0 0 : I/O port P9
7
/DA
0
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
0 : LOW
1 : HIGH
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bit
(Valid only in single-chip
mode)
WAIT peripheral function
clock stop bit
X
CIN
-X
COUT
drive capacity
select bit (Note 2)
Port X
C
select bit
0 : I/O port
1 : X
CIN
-X
COUT
generation
0 : On
1 : Off
0 : CM16 and CM17 valid
1 : Division by 8 mode
Main clock (X
IN
-X
OUT
)
stop bit (Note 3, 4, 5)
Main clock division select
bit 0 (Note 7)
System clock select bit
(Note 6)
0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with X
IN
, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, X
OUT
turns “H”. The built-in feedback resistor remains being connected, so X
IN
turns
pulled up to X
OUT
(“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: f
C32
is not included.
System clock control register 1 (Note 1)
Symbol
CM1
Address
0007
16
When reset
20
16
Bit name
Function
Bit symbol
b7
b6
b5
b4
0
b3
0
b2
0
b1
0
b0
CM10
All clock stop control bit
(Note4)
0 : Clock on
1 : All clocks off (stop mode)
Note 1: Set bit 0 of the protect register (address 000A
16
) to
“1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006
16
) is
“0”. If
“1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, X
OUT
turns “H”, and the built-in feedback resistor is cut off. X
CIN
and X
COUT
turn high-
impedance state.
CM15
X
IN
-X
OUT
drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
W
R
W
R
CM16
CM17
Reserved bit
Always set to
“0”
Reserved bit
Always set to
“0”
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
Reserved bit
Always set to
“0”
Reserved bit
Always set to
“0”
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Figure 18. Clock control registers 0 and 1