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參數(shù)資料
| 型號： | M34W02 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 2Kbit Serial EEPROM with Software Data Protection(2Mb串行EEPROM) |
| 中文描述： | 2Kbit串行EEPROM與軟件數(shù)據(jù)保護（處理器串行EEPROM中） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 152K |
| 代理商： | M34W02 |
Bit
Top /
Bottom
ROW pointer
b7
b6
b5
b4
b3
b2
b1
b0
Protect Register bits
T/B
rp6
rp5
rp4
rp3
rp2
rp1
rp0
Protect Register bits values on delivery
0
0
0
0
0
0
0
0
Table 9. Protect Register Bit Value
b0 to b6:
this is the row pointer value which con-
tains the selected row number. This row number is
used as a memory pointer which will determine the
protected area size.
b7: Top/Bottom:
When b7=0
(
WC=1), the pro-
tected area will be from location 00h to the pointed
row (zone 1). When b6-b0 of the protect register
are all 0, all the memory locations are not write
protected. When b7=1 (WC=1), the protected area
will be from the pointed row to the end of the
memory (zone 2). When b6-b0 of the protect reg-
ister are all 0, all the memory locations are write
protected.
On delivery, the Protect Register is set to 00h (all
bits at ’0’). This specific state allows the Protect
Register to be programmed once even if the WC
input is high. This feature is useful to program the
Protect Register with the M34W02 soldered in the
application. Pin 7 of the M34W02 can be directly
connected to V
CC
. After and only after program-
ming the Protect Register, even with the value 00h,
the WC input (pin 7) will be activated by the
M34W02: the Protect Register and the selected
memory area will be write protected.
It is possible to modify the write protected area by
pulling the WC pin low (see Figure 9).
To modify the Protect Register content, the WC
input must be low. At this time, it is possible to
modify all the 8 bits of the protect register (bit 7
included). This feature allows you to modify the
protected area size and to modify the selected
memory zone by changing the value of bit 7.
Read Operations
Read operations are independent from the state of
the Protect Register and the WC input pin. On
delivery, the memory contents is set at all "1’s" (or
FFh) and the Protect Register at all "0’s" (or 00h).
Current Address Read.
The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
AI01965
FFh
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
b0
b1
b2
b3
b4
b5
b6
1
0
2
3
Not
allowed
15
Row
Number
M34W02
Memory
EFh
F0h
E0h
2Fh
1Fh
20h
10h
0Fh
00h
Figure 8. Protected Area Size
the master sends a device select code with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master must NOT acknowledge the byte out-
put and must terminate the transfer with a STOP
condition.
It is possible, when the WC input pin is low, to read
the contents of the protect register. In this case,
after the START condition, the device select code
must have the 4 device type identifier bits set to
0110b. When the WC input pin is high, it is not
possible to read the protect register.
Random Address Read.
A dummy write is per-
formed to load the memory address into the ad-
dress counter, see Figure 11. This is followed by
another START condition from the master and the
device select code is repeated with the RW bit set
to ’1’. The memory acknowledges this and outputs
the byte addressed. The master must NOT ac-
knowledge the byte output and must terminate the
transfer with a STOP condition.
DEVICE OPERATIONS
(cont’d)
10/17
M34W02
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