參數(shù)資料
型號： M34W02
廠商： 意法半導體
元件分類： DRAM
英文描述： 2Kbit Serial EEPROM with Software Data Protection(2Mb串行EEPROM)
中文描述： 2Kbit串行EEPROM與軟件數(shù)據(jù)保護（處理器串行EEPROM中）
文件頁數(shù)： 7/17頁
文件大?。?/td> 152K
代理商： M34W02
SCL
SDA IN
SCL
SDA OUT
SCL
SDA IN
tCHCL
tDLCL
tCHDX
START
CONDITION
tCLCH
tDXCX
tCLDX
SDA
INPUT
SDA
CHANGE
tCHDH
tDHDL
STOP &
BUS FREE
DATA VALID
tCLQV
tCLQX
DATA OUTPUT
tDHDL
tCHDH
STOP
CONDITION
tCHDX
START
CONDITION
WRITE CYCLE
tW
AI00795
Figure 5. AC Waveforms
each acknowledged by the memory if the ad-
dressed row is not write protected. If the addressed
row is write protected, each data byte is followed
by a NoACK and the locations will not be modified.
After each byte is transferred, the internal byte
address counter (4 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition.
Care must be taken to avoid address counter ’roll-
over’ which could result in data being overwritten.
Note that, for any byte or page write mode, the
generation by the master of the STOP condition
starts the internal memory program cycle. All inputs
are disabled until the completion of this cycle and
the memory will not respond to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t
W
) is given in the
AC Characteristics table. Since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master.
7/17
M34W02
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