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參數(shù)資料
| 型號(hào)： | M34W02 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 2Kbit Serial EEPROM with Software Data Protection(2Mb串行EEPROM) |
| 中文描述： | 2Kbit串行EEPROM與軟件數(shù)據(jù)保護(hù)（處理器串行EEPROM中） |
| 文件頁數(shù)： | 2/17頁 |
| 文件大小： | 152K |
| 代理商： | M34W02 |
The M34W02 is manufactured in SGS-THOM-
SON’s Hi-Endurance Advanced CMOS technol-
ogy. The memories operate with a power supply
value as low as 1.8V for the M34W02-R.
Plastic Dual In-line, Plastic Small Outline and Thin
Shrink Small Outline packages are available.
The memory is compatible with the I
2
C standard,
two-wire serial interface which uses a bi-directional
data bus and serial clock. The memories carry two
built-in 4-bit device identification codes: ’1010’
which corresponds to the I
2
C bus definition to
access the memory area and ’0110’ to access the
additional Protect Register. These codes are used
together with 3 chip enable inputs (E2, E1, E0) so
that up to eight 2K bit devices may be attached to
SDA
VSS
SCL
WC
E1
E2
E0
VCC
AI01961
M34W02
1
2
3
4
8
7
6
5
Figure 2A. DIP Pin Connections
1
2
3
4
AI01962
8
7
6
5
SDA
VSS
SCL
WC
E1
E2
E0
VCC
M34W02
Figure 2B. SO and TSSOP Pin Connections
DESCRIPTION
(cont’d)
Symbol
Parameter
Value
Unit
T
A
Ambient OperatingTemperature
(2)
–40 to 85
°
C
T
STG
Storage Temperature
–65 to 150
°
C
T
LEAD
Lead Temperature, Soldering
(PSDIP8 package)
(SO8 package)
(TSSOP8 package)
10 sec
40 sec
t.b.c.
260
215
t.b.c.
°
C
V
IO
Input or Output Voltages
–0.6 to 6.5
V
V
CC
Supply Voltage
–0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
(3)
4000
V
Electrostatic Discharge Voltage (Machine model)
(4)
500
V
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. Depends on range.
3. MIL-STD-883C, 3015.7 (100pF, 1500
).
4. EIAJ IC-121 (Condition C) (200pF, 0
).
Table 2. Absolute Maximum Ratings
(1)
the I
2
C bus and selected individually. The memory
behaves as a slave device in the I
2
C protocol with
all memory operations synchronized by the serial
clock. Read and write operations are initiated by a
START condition generated by the bus master. The
START condition is followed by a stream of 7 bits
(identification code ’1010’ or ’0110’ followed by the
3 chip enable bits), plus one read/write bit (RW) and
terminated by an acknowledge bit.
When writing data to the memory, it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition after an Ack for
WRITE and after a NoAck for a READ.
2/17
M34W02
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