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參數(shù)資料
| 型號(hào)： | M34W02 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 2Kbit Serial EEPROM with Software Data Protection(2Mb串行EEPROM) |
| 中文描述： | 2Kbit串行EEPROM與軟件數(shù)據(jù)保護(hù)（處理器串行EEPROM中） |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 152K |
| 代理商： | M34W02 |
AI01115
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
25
50
75
100
0
4
8
12
16
20
CBUS (pF)
R
)
VCC = 5V
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus, fc = 400KHz
DEVICE OPERATION
I
2
C Bus Background
The M34W02 supports the I
2
C protocol. This pro-
tocol defines any device that sends data onto the
bus as a transmitter and any device that reads the
data as a receiver. The device that controls the data
transfer is known as the master and the other as
the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The M34W02 is always a slave de-
vice in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the M34W02 continu-
ously monitors the SDA and SCL signals for a
START condition and will not respond unless a
START condition is given.
Stop Condition.
STOP is identified by a low to
high transition of the SDA line while the clock SCL
is stable in the high state. A STOP condition termi-
nates communication between the M34W02 and
the bus master. A STOP condition at the end of a
Read sequence, after and only after a No-Acknow-
ledge, forces the standby state. A STOP condition
at the end of a Write command triggers the internal
EEPROM write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input.
During data input the M34W02 sam-
ples the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation,
the SDA signal must be stable during the clock low
to high transition and the data must change ONLY
when the SCL line is low.
Memory Addressing.
To start communication
between the bus master and the slave M34W02,
the master must initiate a START condition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I
2
C bus definition. For this memory the 4 bits are
fixed as 1010b to access the memory area and as
0110b to access the Protect Register. The following
3 bits identify the specific memory on the bus. They
are matched to the external chip enable signals E2,
E1, E0. Thus up to eight 2K memories can be
connected on the same bus giving a memory ca-
pacity total of 16K bits. After a START condition any
4/17
M34W02
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