Rev.2.00
Nov 23, 2005
page 28 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 24 Structure of Timer 1 to timer 4 related registers
Timer 12 mode register
(T12M: address 002516)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
b3 b2
00 : Frequency divider for Timer 1
01 : f(XCIN)
10 : Underflow of Timer Y
11 : Not available
Timer 2 count source selection bits
b5 b4
00 : Underflow of Timer 1
01 : f(XCIN)
10 : Frequency divider for Timer 2
11 : Not available
Timer 2 output selection bit (P72)
0 : I/O port
1 : Timer 2 output
T2OUT output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer 34 mode register
(T34M: address 002616)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bit
0 : Frequency divider for Timer 3
1 : Underflow of Timer 2
Timer 4 count source selection bits
b4 b3
0 0 : Frequency divider for Timer 4
0 1 : Underflow of Timer 3
1 0 : Underflow of Timer 2
1 1 : f(XIN)
Timer 3 operating mode selection bit
0 : Timer mode
1 : PWM mode
Timer 4 operating mode selection bit
0 : Timer mode
1 : PWM mode
Not used (returns “0” when read)
Timer 1234 mode register
(T1234M: address 002716)
T3OUT output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
T4OUT output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer 3 output selection bit (P73)
0 : I/O port
1 : Timer 3 output
Timer 4 output selection bit (P74)
0 : I/O port
1 : Timer 4 output
Timer 2 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 3 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 4 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Not used (returns “0” when read)
b7
b0
b7
b0
b7
b0
PWM01 register
(PWM01: address 002416)
PWM0 set bits
b1 b0
00 : No extended
01 : Extended once in four periods
10 : Extended twice in four periods
11 : Extended three times in four periods
PWM1 set bits
b3 b2
00 : No extended
01 : Extended once in four periods
10 : Extended twice in four periods
11 : Extended three times in four periods
Not used (returns “0” when read)
Timer 1234 frequency division selection register
(PRE1234: address 002816)
Timer 1 frequency division selection bits
b1 b0
0 0 : 1/16
φ SOURCE
0 1 : 1/1
φ SOURCE
1 0 : 1/2
φ SOURCE
1 1 : 1/256
φ SOURCE
Timer 2 frequency division selection bits
b3 b2
0 0 : 1/16
φ SOURCE
0 1 : 1/1
φ SOURCE
1 0 : 1/2
φ SOURCE
1 1 : 1/256
φ SOURCE
Timer 3 frequency division selection bits
b5 b4
0 0 : 1/16
φ SOURCE
0 1 : 1/1
φ SOURCE
1 0 : 1/2
φ SOURCE
1 1 : 1/256
φ SOURCE
Timer 4 frequency division selection bits
b7 b6
0 0 : 1/16
φ SOURCE
0 1 : 1/1
φ SOURCE
1 0 : 1/2
φ SOURCE
1 1 : 1/256
φ SOURCE
b7
b0
b7
b0
φ SOURCE: represents the oscillation frequency of
XIN input in the middle- and high-speed mode,
on-chip oscillator divided by 4 in the on-chip
oscillator mode,
and sub-clock in the low-speed mode.
Note: