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參數(shù)資料
| 型號(hào)： | M38C59GFHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 6.25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 30/71頁 |
| 文件大小： | 939K |
| 代理商： | M38C59GFHP |
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Rev.2.00
Nov 23, 2005
page 36 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by set-
ting the serial I/O mode selection bit of the serial I/O1 control register
to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift regis-
ter cannot be written to or read from directly, transmit data is written
to the transmit buffer register, and receive data is read from the re-
ceive buffer register.
The transmit buffer register can also hold the next data to be trans-
mitted, and the receive buffer register can hold a character while the
next character is being received.
Fig. 32 Block diagram of UART serial I/O1
Fig. 33 Operation of UART serial I/O1 function
1/4
OE
PE FE
1/16
Data bus
Receive buffer register
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Transmit buffer register
Data bus
Transmit shift register
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
ST detector
SP detector
UART control register
Address 001B16
Character length selection bit
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O1 synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O1 control register
Serial I/O1 status register
Address 001816
Address 001C16
Address 001816
Address 001916
Address 001A16
P40/RXD
P42/SCLK1
P41/TXD
φSOURCE
φ SOURCE:represents the supply source of internal clock φ.
XIN input: in the middle- or high-speed mode,
Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and
Sub clock in the low-speed mode.
TSC=0
TBE=1
RBF=0
TBE=0TBE=0
RBF=1
ST
D0
D1
SP
D0
D1
ST
SP
TBE=1
TSC=1
ST
D0
D1
SP
D0
D1
ST
SP
Transmit or receive clock
Transmit buffer register
write signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC flag =“1”, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC flag = “0”.
Notes
Serial output TXD
Serial input RXD
Receive buffer register
read signal
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