參數(shù)資料
型號: M38C59GFHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 47/71頁
文件大小: 939K
代理商: M38C59GFHP
Rev.2.00
Nov 23, 2005
page 51 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
CLOCK OUTPUT FUNCTION
A system clock
φ can be output from I/O port P72.The triple function
of I/O port, timer 2 output function and system clock
φ output func-
tion are controlled by the clock output control register (address
0FF316) and the timer 2 output selection bit of the timer 12 mode
register (address 002516).
In order to output a system clock
φ from I/O port P72, set the timer 2
output selection bit to “1“ and P72 clock output control bits of the
clock output control register to “01”. In order to output the same sig-
nal as oscillation frequency of sub clock XCIN, set the P72 clock out-
put control bits to “10”. When the clock output function is selected, a
clock is output while the direction register of port P72 is set to the
output mode.
P72 is switched to the port output or the output (timer 2 output or the
clock output) except port at the cycle after the P72 clock output con-
trol bits are switched.
Fig. 49 Block diagram of Clock output function
Fig. 48 Structure of clock output control register
b7
b0
Clock output control register
(CKOUT : address 0FF316)
P72 clock output control bits
b1b0
0 0: Timer 2 output
0 1:
φ frequency signal output
1 0: XCIN frequency signal output
1 1: Not available
Not used (returns “0” when read)
(Do not write “1” to these bits.)
1/2
Q
S
T
“0”
“1”
P72/T2OUT/CKOUT
P72 clock output
control bits
b7
b0
System clock
φ
XCIN
“00”
“01”
“10”
Timer 2 latch (8)
Timer 2 (8)
T2OUT output
edge switch bit
P72 clock output control bits
P72 latch
Timer 2 output selection bit
P72 direction register
Timer 12 mode register (address 002516)
T12M
Timer 2 output selection bit
0: I/O port
1: Timer 2 output
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