參數(shù)資料
型號(hào)： M38C59GFHP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 69/71頁(yè)
文件大?。?/td> 939K
代理商： M38C59GFHP
Rev.2.00
Nov 23, 2005
page 71 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
A/D Converter Characteristics
Table 18 A/D converter recommended operating condition
(Vcc = 2.0 to 3.6 V, Ta = –20 to 85°C, output transistors in cut-off state, unless otherwise noted)
Power source voltage
“H” input voltage ADKEY0
“L” input voltage ADKEY0
AD converter control clock
(Note)
(Low-speed on-chip oscillator
mode excluded)
Unit
V
MHz
Limits
Parameter
Min.
2.0
0.9Vcc
0
Typ.
Max.
3.6
Vcc
0.7 VCC–0.5
20 Vcc–38
45 Vcc–35
8
12.5
Symbol
VCC
≤ 2.2 V
2.2 V < VCC
≤ 3.0 V
3.0 V < VCC
≤ 3.6 V
Test conditions
Note: Confirm the recommended opearting condition for main clock input frequency.
Table 19 A/D converter characteristics
(Vcc = 2.0 to 3.6 V, Ta = –20 to 85°C, output transistors in cut-off state, low-speed on-chip oscillator mode included, unless otherwise noted)
VCC
VIH
VIL
f(XIN)
Resolution
Absolute accuracy
(quantification error excluded)
Unit
Bits
LSB
s
k
A
Limits
Parameter
Min.
12
30
Typ.
35
100
Max.
10
4
2
tc(
φAD)121
(Note)
100
130
5.0
Symbol
2.5 < VCC
≤ 3.6, f(XIN) ≤ 6 MHz
AD conversion clock =
φSOURCE/2
10bitAD mode
2.2 < VCC
≤ 2.5, f(XIN) ≤ 12.5 MHz
or Low-speed mode on-chip oscillator mode
AD conversion clock =
φSOURCE/2
10bitAD mode
3.0 < VCC
≤ 3.6, f(XIN) ≤ 12.5 MHz
AD conversion clock =
φSOURCE/8
8bitAD mode
2.2 < VCC
≤ 3.0, f(XIN) ≤ 8 MHz
AD conversion clock =
φSOURCE/8
8bitAD mode
2.0 < VCC
≤ 2.2, f(XIN) ≤ 6 MHz
AD conversion clock =
φSOURCE/8
or Low-speed mode on-chip oscillator mode
AD conversion clock =
φSOURCE/2
8bitAD mode
AD conversion clock =
φSOURCE/2
10bitAD mode
VREF = 3.3 V
Test conditions
—
ABS
Resolution
Absolute accuracy
(quantification error excluded)
Conversion time
Ladder resistor
Reference input current
Analog input current
—
ABS
Tconv
RLADDER
IVREF
IIA
Note: When “
φSOURCE/8” is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 4.
The operation clock is XIN in the middle- or high-speed mode, or the on-chip oscillator in the other modes.
When the A/D conversion is executed in the middle- or high-speed mode, set f(XIN)
≤ 500 kHz.
tc(
φAD): One cycle of control clock for A/D converter. XIN input is used in the middel- or high-speed mode, and on-chip oscillator is used in the low- or on-chip
oscillator mode for the control clock.
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