Rev.2.00
Nov 23, 2005
page 32 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
(4) Set of Timer X Mode Register
Set the write control bit of the timer X mode register to “1” (write to
the latch only) when setting the IGBT output and PWM modes.
Output waveform simultaneously reflects the contents of both regis-
ters at the next underflow after writing to the timer X register (high-
order).
(5) Output Control Function of Timer X
When using the output control function (INT1 and INT2) in the IGBT
output mode, set the levels of INT1 and INT2 to “H” in the falling
edge active or to “L” in the rising edge active before switching to the
IGBT output mode.
(6) Switch of CNTR0 Active Edge
When the CNTR0 active edge switch bits are set, at the same time,
the interrupt active edge is also affected.
When the pulse width is measured, set the bit 7 of the CNTR0 ac-
tive edge switch bits to “0”.
Fig. 27 Structure of Timer X related registers
Timer X mode register
(TXM: address 002D16)
Timer X operating mode bits
b2 b1 b0
0 0 0 : Timer mode
0 0 1 : Pulse output mode
0 1 0 : IGBT output mode
0 1 1 : PWM mode
1 0 0 : Event counter mode
1 0 1 : Pulse width measurement mode
1 1 0 : Not available
1 1 1 : Not available
b7
b0
Timer X control register 1
(TXCON1: address 002E16)
Noise filter sampling clock selection bit
0 : f(XIN)/2
1 : f(XIN)/4
b7
b0
Timer X output 2 selection bit (P63)
0 : I/O port
1 : Timer X output 2
b7
b0
φ SOURCE: represents the supply source of internal clock φ.
XIN input: in the middle- or high-speed mode,
Internal on-chip oscillator divided by 4 in the on-chip
oscillator mode, and
Sub clock in the low-speed mode.
Timer X control register 2
(TXCON2: address 002F16)
Not used (returns “0” when read)
Trigger for IGBT input control bit
0 : Noise filter sampling clock 1
External trigger delay time 1
1 : Noise filter sampling clock 2
External trigger delay time 1/2
Timer X diving frequency selection bits
b3 b2
00 : 1/16
φ SOURCE
01 : 1/1
φ SOURCE (Note)
10 : 1/2
φ SOURCE
11 : 1/256
φ SOURCE
Timer X output 2 active edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer X output 1 selection bit (P65)
0 : I/O port
1 : Timer X output 1
Timer X count stop bit
0 : Count operation
1 : Count stop
Data for control of event counter window
0 : Event count enabled
1 : Event count disabled
Timer X count source selection bit
0 : Frequency divider output
1 : f(XCIN)
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
CNTR0 active edge switch bits
b7 b6
0 0 : Count at rising edge in event counter mode
Falling edge active for CNTR0 interrupt
Measure “H” pulse width in pulse width measurement mode
0 1 : Count at falling edge in event counter mode
Rising edge active for CNTR0 interrupt
Measure “L” pulse width in pulse width measurement mode
10 :
11 :
Timer X output 1 edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer X output 2 control bit (P64)
0 : Not used
1 : INT2 interrupt used
Timer X output 1 control bit (P66 or P71)
0 : Not used
1 : INT1 interrupt used
External trigger delay time selection bits
b2 b1
0 0 : Not delayed
0 1 : (4/f(XIN))
s
1 0 : (8/f(XIN))
s
1 1 : (16/f(XIN))
s
Count at both edges in event counter mode
Both edges active for CNTR0 interrupt