M48Z129Y, M48Z129V
2/13
Figure 2A. DIP Pin Connections
A1
A0
DQ0
DQ1
DQ2
VSS
A7
A6
A5
A4
A3
A2
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
A15
BL
DQ5
DQ4
DQ3
A16
A14
RST
VCC
AI02310
M48Z129Y
M48Z129V
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A12
W
32
31
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2.
Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°C
T
STG
Storage Temperature (V
CC
Off)
–40 to 70
°C
T
BIAS
Temperature Under Bias
–10 to 70
°C
T
SLD (2)
Lead Solder Temperature for 10 seconds
260
°C
V
IO
Input or Output Voltages
–0.3 to V
CC
+0.3
V
V
CC
Supply Voltage
M48Z129Y
M48Z129V
–0.3 to 7.0
–0.3 to 4.6
V
DESCRIPTION
The M48Z129Y/V ZEROPOWER SRAM is a
1,048,576 bit non-volatile static RAM organized as
131,072 words by 8 bits. The device combines an
internal lithium battery, a CMOS SRAM and a con-
trol circuit in a plastic 32 pin DIP Module. The
M48Z129Y/V directly replaces industry standard
128K x 8 SRAM. It also provides the non-volatility
of FLASH without any requirement for special
write timing or limitations on the number of writes
that can be performed.
The M48Z129Y/V also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing data security in
the midst of unpredictable system operation. As
V
CC
falls, the control circuitry automatically switch-
es to the battery, maintaining data until valid power
is restored.
READ MODE
The M48Z129Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within t
AVQV
(Ad-
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (t
ELQV
)
or Output Enable Access Time (t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for t
AXQX
(Output
Data Hold Time) but will go indeterminate until the
next Address Access.